Inventor · disambiguated record
Alexander H. Owens
Also filed as: OWENS ALEXANDER H
22 granted patents·576 citations·filing 1984–2013
96Inventor score
Files withNAT SEMICONDUCTOR CORP6LSI LOGIC CORP5SOLID STATE SCIENT3SPRAGUE ELECTRIC CO3ALLEGRO MICROSYSTEMS INC2
Top patents by PatentIndex Score
22 records- 0192US5612552AMultilevel gate array integrated circuit structure with perpendicular access to all active device regionsLSI LOGIC CORP·Filed 1995·Granted Mar 18, 1997·119 cites·17 claims
- 0288US7795126B2Electrical die contact structure and fabrication methodNAT SEMICONDUCTOR CORP·Filed 2008·Granted Sep 14, 2010·12 cites·24 claims
- 0383US4598460AMethod of making a CMOS EPROM with independently selectable thresholdsSOLID STATE SCIENT·Filed 1984·Granted Jul 8, 1986·38 cites·10 claims
- 0482US8765534B2Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatusNAT SEMICONDUCTOR CORP·Filed 2013·Granted Jul 1, 2014·5 cites·4 claims
- 0582US5220192ARadiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereofLSI LOGIC·Filed 1992·Granted Jun 15, 1993·66 cites·12 claims
- 0679US5998280AModified recessed locos isolation process for deep sub-micron device processesNAT SEMICONDUCTOR CORP·Filed 1998·Granted Dec 7, 1999·57 cites·16 claims
- 0778US4646425AMethod for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layerSOLID STATE SCIENT·Filed 1984·Granted Mar 3, 1987·31 cites·14 claims
- 0872US6946706B1LDMOS transistor structure for improving hot carrier reliabilityNAT SEMICONDUCTOR CORP·Filed 2003·Granted Sep 20, 2005·19 cites·16 claims
- 0970US8395216B2Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatusOWENS ALEXANDER H·Filed 2009·Granted Mar 12, 2013·5 cites·14 claims
- 1070US4914051AMethod for making a vertical power DMOS transistor with small signal bipolar transistorsSPRAGUE ELECTRIC CO·Filed 1988·Granted Apr 3, 1990·28 cites·8 claims
- 1168US5621616AHigh density CMOS integrated circuit with heat transfer structure for improved coolingLSI LOGIC CORP·Filed 1995·Granted Apr 15, 1997·37 cites·20 claims
- 1265US4590665AMethod for double doping sources and drains in an EPROMSOLID STATE SCIENT·Filed 1984·Granted May 27, 1986·27 cites·3 claims
- 1361US7340181B1Electrical die contact structure and fabrication methodNAT SEMICONDUCTOR CORP·Filed 2002·Granted Mar 4, 2008·7 cites·11 claims
- 1457US6586302B1Method of using trenching techniques to make a transistor with a floating gateNAT SEMICONDUCTOR CORP·Filed 2001·Granted Jul 1, 2003·8 cites·8 claims
- 1556US5091321AMethod for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuitALLEGRO MICROSYSTEMS INC·Filed 1991·Granted Feb 25, 1992·18 cites·7 claims
- 1656US4774202AMemory device with interconnected polysilicon layers and method for makingSPRAGUE ELECTRIC CO·Filed 1987·Granted Sep 27, 1988·24 cites·8 claims
- 1750US5516731AHigh-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistanceLSI LOGIC CORP·Filed 1994·Granted May 14, 1996·21 cites·12 claims
- 1846US5661069AMethod of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve spaceLSI LOGIC CORP·Filed 1995·Granted Aug 26, 1997·10 cites·1 claims
- 1944US6579777B1Method of forming local oxidation with sloped silicon recessCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jun 17, 2003·12 cites·20 claims
- 2041US5561319AIntegrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereofLSI LOGIC CORP·Filed 1994·Granted Oct 1, 1996·12 cites·25 claims
- 2141US5045492AMethod of making integrated circuit with high current transistor and CMOS transistorsALLEGRO MICROSYSTEMS INC·Filed 1989·Granted Sep 3, 1991·11 cites·9 claims
- 2236US4706102AMemory device with interconnected polysilicon layers and method for makingSPRAGUE ELECTRIC CO·Filed 1985·Granted Nov 10, 1987·9 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →