Inventor · disambiguated record
Janmye Sung
Also filed as: SUNG JANMYE
34 granted patents·1,473 citations·filing 1989–1999
98Inventor score
Files withVANGUARD INT SEMICONDUCT CORP19AT & T BELL LAB7LUCENT TECHNOLOGIES INC4AT & T CORP3VANGAURD INTERNATIONAL SEMICON1
Top patents by PatentIndex Score
34 records- 0198US5943581AMethod of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuitsVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Aug 24, 1999·322 cites·26 claims
- 0293US5559360AInductor for high frequency circuitsLUCENT TECHNOLOGIES INC·Filed 1994·Granted Sep 24, 1996·86 cites·14 claims
- 0392US5858831AProcess for fabricating a high performance logic and embedded dram devices on a single semiconductor chipVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jan 12, 1999·118 cites·24 claims
- 0491US5153145AFet with gate spacerAT & T BELL LAB·Filed 1989·Granted Oct 6, 1992·61 cites·5 claims
- 0589US5879986AMethod for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum featureVANGAURD INTERNATIONAL SEMICON·Filed 1998·Granted Mar 9, 1999·76 cites·22 claims
- 0687US6136643AMethod for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technologyVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Oct 24, 2000·76 cites·22 claims
- 0787US5547893Amethod for fabricating an embedded vertical bipolar transistor and a memory cellVANGUARD INT SEMICONDUCT CORP·Filed 1995·Granted Aug 20, 1996·77 cites·30 claims
- 0884US5550078AReduced mask DRAM processVANGUARD INT SEMICONDUCT CORP·Filed 1995·Granted Aug 27, 1996·63 cites·24 claims
- 0983US6180453B1Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squaredVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jan 30, 2001·53 cites·24 claims
- 1083US6008084AMethod for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitanceVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Dec 28, 1999·74 cites·22 claims
- 1180US5792680AMethod of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitorVANGUARD INT SEMICONDUCT CORP·Filed 1996·Granted Aug 11, 1998·44 cites·22 claims
- 1279US5753551AMemory cell array with a self-aligned, buried bit lineVANGUARD INT SEMICONDUCT CORP·Filed 1996·Granted May 19, 1998·41 cites·25 claims
- 1379US5679589AFET with gate spacerLUCENT TECHNOLOGIES INC·Filed 1992·Granted Oct 21, 1997·38 cites·4 claims
- 1478US6008085ADesign and a novel process for formation of DRAM bit line and capacitor node contactsVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Dec 28, 1999·39 cites·23 claims
- 1577US5821142AMethod for forming a capacitor with a multiple pillar structureVANGUARD INT SEMICONDUCT CORP·Filed 1996·Granted Oct 13, 1998·35 cites·17 claims
- 1669US5789291ADram cell capacitor fabrication methodVANGUARD INT SEMICONDUCT CORP·Filed 1995·Granted Aug 4, 1998·26 cites·23 claims
- 1769US5470783AMethod for integrated circuit device isolationAT & T CORP·Filed 1995·Granted Nov 28, 1995·47 cites·10 claims
- 1868US6025227ACapacitor over bit line structure using a straight bit line shapeVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Feb 15, 2000·21 cites·24 claims
- 1964US5573962ALow cycle time CMOS processVANGUARD INT SEMICONDUCT CORP·Filed 1995·Granted Nov 12, 1996·22 cites·30 claims
- 2062US6137130ACapacitor over bit line structure using a straight bit line shapeVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Oct 24, 2000·16 cites·4 claims
- 2160US6163047AMethod of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cellVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Dec 19, 2000·17 cites·28 claims
- 2257US5808335AReduced mask DRAM processVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Sep 15, 1998·15 cites·1 claims
- 2351US5353245AMemory integrated circuit with balanced resistanceAT & T BELL LAB·Filed 1993·Granted Oct 4, 1994·13 cites·3 claims
- 2450US6198121B1Method fabricating a DRAM cell with an area equal to four times the used minimum featureVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Mar 6, 2001·9 cites·6 claims
- 2550US4999317AMetallization processingAT & T BELL LAB·Filed 1989·Granted Mar 12, 1991·16 cites·17 claims
- 2649US5879997AMethod for forming self aligned polysilicon contactLUCENT TECHNOLOGIES INC·Filed 1991·Granted Mar 9, 1999·12 cites·4 claims
- 2746US5002898AIntegrated-circuit device isolationAT & T BELL LAB·Filed 1989·Granted Mar 26, 1991·13 cites·11 claims
- 2845US5729056ALow cycle time CMOS processVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Mar 17, 1998·8 cites·3 claims
- 2941US5488248AMemory integrated circuitAT & T CORP·Filed 1995·Granted Jan 30, 1996·6 cites·3 claims
- 3040US4935376AMaking silicide gate level runnersAT & T BELL LAB·Filed 1989·Granted Jun 19, 1990·7 cites·7 claims
- 3134US5656510AMethod for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current controlLUCENT TECHNOLOGIES INC·Filed 1994·Granted Aug 12, 1997·8 cites·14 claims
- 3234US5128738AIntegrated circuitAT & T BELL LAB·Filed 1991·Granted Jul 7, 1992·6 cites·4 claims
- 3330US5334541AMethod of fabricating an integrated circuit with lines of critical width extending in the astigmatically preferred direction of the lithographic toolAT & T BELL LAB·Filed 1992·Granted Aug 2, 1994·2 cites·2 claims
- 3429US5462888AProcess for manufacturing semiconductor BICMOS deviceAT & T CORP·Filed 1994·Granted Oct 31, 1995·6 cites·7 claims
Join the waitlist — get patent alerts
Get an alert when Janmye Sung files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →