Inventor · disambiguated record
Yong Meng Lee
Also filed as: LEE YONG M · LEE YONG MENG · LEUNG YING-KEUNG
43 granted patents·16 pending applications·570 citations·filing 1998–2025
98Inventor score
Files withCHARTERED SEMICONDUCTOR MFG20IBM10GLOBALFOUNDRIES INC9POET TECH INC8GLOBALFOUNDRIES SG PTE LTD3
Top patents by PatentIndex Score
59 records- 0192US9524911B1Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 20, 2016·18 cites·16 claims
- 0292US6025267ASilicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devicesCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Feb 15, 2000·140 cites·27 claims
- 0391US7737009B2Method of implanting a non-dopant atom into a semiconductor deviceINFINEON TECHNOLOGIES AG·Filed 2007·Granted Jun 15, 2010·16 cites·16 claims
- 0491US7445978B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 4, 2008·22 cites·31 claims
- 0591US2025347741A1Structure and method for testing of pic with an upturned mirrorPOET TECH INC·Filed 2025·Application pending·0 cites
- 0689US7309637B2Method to enhance device performance with selective stress reliefCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Dec 18, 2007·14 cites·26 claims
- 0788US6511884B1Method to form and/or isolate vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 28, 2003·48 cites·27 claims
- 0888US2025020716A1Structure and method for testing of pic with an upturned mirrorPOET TECH INC·Filed 2024·Application pending·0 cites
- 0987US7193254B2Structure and method of applying stresses to PFET and NFET transistor channels for improved performanceCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Mar 20, 2007·37 cites·9 claims
- 1086US12366603B1Structure and method for testing of PIC with an upturned mirrorPOET TECH INC·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 1185US7893502B2Threshold voltage improvement employing fluorine implantation and adjustment oxide layerIBM·Filed 2009·Granted Feb 22, 2011·12 cites·17 claims
- 1285US6372569B1Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performanceCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 16, 2002·47 cites·27 claims
- 1384US7977185B2Method and apparatus for post silicide spacer removalIBM·Filed 2005·Granted Jul 12, 2011·9 cites·14 claims
- 1484US7256084B2Composite stress spacerCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 14, 2007·12 cites·19 claims
- 1583US6927104B2Method of forming double-gated silicon-on-insulator (SOI) transistors with corner roundingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Aug 9, 2005·32 cites·48 claims
- 1681US6835609B1Method of forming double-gate semiconductor-on-insulator (SOI) transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 28, 2004·31 cites·52 claims
- 1779US9385030B2Spacer to prevent source-drain contact encroachmentGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 5, 2016·4 cites·12 claims
- 1878US7659174B2Method to enhance device performance with selective stress reliefCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Feb 9, 2010·6 cites·18 claims
- 1978US7141854B2Double-gated silicon-on-insulator (SOI) transistors with corner roundingCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 28, 2006·7 cites·27 claims
- 2077US7442611B2Method of applying stresses to PFET and NFET transistor channels for improved performanceIBM·Filed 2007·Granted Oct 28, 2008·6 cites·7 claims
- 2177US7393746B2Post-silicide spacer removalIBM·Filed 2006·Granted Jul 1, 2008·6 cites·6 claims
- 2274US12105141B2Structure and method for testing of PIC with an upturned mirrorPOET TECH INC·Filed 2021·Granted Oct 1, 2024·0 cites·20 claims
- 2374US11921156B2Structure and method for testing of PIC with an upturned mirrorPOET TECH INC·Filed 2021·Granted Mar 5, 2024·0 cites·20 claims
- 2472US2024004148A1Reflector structure having three-dimensional curvaturePOET TECH INC·Filed 2023·Application pending·0 cites
- 2572US2024004147A1Reflector structure having three-dimensional curvaturePOET TECH INC·Filed 2023·Application pending·0 cites
- 2671US9607989B2Forming self-aligned NiSi placement with improved performance and yieldGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 28, 2017·2 cites·18 claims
- 2771US8624329B2Spacer-less low-K dielectric processesLEE YONG MENG·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 2870US7598572B2Silicided polysilicon spacer for enhanced contact areaIBM·Filed 2006·Granted Oct 6, 2009·4 cites·2 claims
- 2969US8716081B2Capacitor top plate over source/drain to form a 1T memory deviceTEO LEE WEE·Filed 2007·Granted May 6, 2014·4 cites·29 claims
- 3069US8274115B2Hybrid orientation substrate with stress layerTEO LEE WEE·Filed 2008·Granted Sep 25, 2012·4 cites·16 claims
- 3169US7999325B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·3 cites·20 claims
- 3268US7615427B2Spacer-less low-k dielectric processesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 10, 2009·3 cites·20 claims
- 3368US6787404B1Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitanceCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Sep 7, 2004·15 cites·49 claims
- 3467US9202697B2Forming a gate by depositing a thin barrier layer on a titanium nitride capGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 1, 2015·2 cites·11 claims
- 3566US8053327B2Method of manufacture of an integrated circuit system with self-aligned isolation structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Nov 8, 2011·3 cites·10 claims
- 3666US6583011B1Method for forming damascene dual gate for improved oxide uniformity and controlCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 24, 2003·15 cites·33 claims
- 3763US6258648B1Selective salicide process by reformation of silicon nitride sidewall spacersCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 10, 2001·19 cites·8 claims
- 3863US2025133865A1Solder bridge metallization using solder ball jettingPOET TECH INC·Filed 2024·Application pending·0 cites
- 3961US7396724B2Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicalsIBM·Filed 2005·Granted Jul 8, 2008·2 cites·18 claims
- 4058US6436754B1Selective salicide process by reformation of silicon nitride sidewall spacersCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 20, 2002·7 cites·5 claims
- 4157US9123783B2Integrated circuits and methods of forming integrated circuits with interlayer dielectric protectionGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 1, 2015·1 cites·16 claims
- 4253US2008128834A1Hot carrier degradation reduction using ion implantation of silicon nitride layerIBM·Filed 2008·Application pending·0 cites
- 4351US8623714B2Spacer protection and electrical connection for array devicePARK JAE-EUN·Filed 2010·Granted Jan 7, 2014·1 cites·15 claims
- 4449US6107140AMethod of patterning gate electrode conductor with ultra-thin gate oxideCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 22, 2000·13 cites·32 claims
- 4548US2006151843A1Hot carrier degradation reduction using ion implantation of silicon nitride layerIBM·Filed 2005·Application pending·0 cites
- 4647US2010009527A1Integrated circuit system employing single mask layer technique for well formationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 4745US9147572B2Using sacrificial oxide layer for gate length tuning and resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·0 cites·12 claims
- 4845US2008315317A1Semiconductor system having complementary strained channelsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 4944US9209258B2Depositing an etch stop layer before a dummy cap layer to improve gate performanceGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 8, 2015·0 cites·16 claims
- 5042US2016049488A1Semiconductor gate with wide top or bottomGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
Showing the top 50 of 59 patent records by PatentIndex Score.
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