Inventor · disambiguated record
Jaegeun Yun
Also filed as: YUN JAEGEUN
11 granted patents·4 pending applications·34 citations·filing 2010–2025
87Inventor score
Top patents by PatentIndex Score
15 records- 0188US9886414B2Bus system in SoCSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Feb 6, 2018·6 cites·20 claims
- 0282US8667195B2Bus-system including an interconnector, a master device, a slave device, and an operating method thereofJEONG BUB-CHUL·Filed 2011·Granted Mar 4, 2014·7 cites·21 claims
- 0377US9152213B2Bus system in SoC and method of gating root clocks thereforYUN JAEGEUN·Filed 2012·Granted Oct 6, 2015·4 cites·17 claims
- 0476US8819310B2System-on-chip and data arbitration method thereofJEONG BUB-CHUL·Filed 2011·Granted Aug 26, 2014·6 cites·15 claims
- 0572US10671562B2Clock gating circuitSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jun 2, 2020·1 cites·15 claims
- 0672US10185684B2System interconnect and operating method of system interconnectSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jan 22, 2019·2 cites·7 claims
- 0772US2025328479A1Semiconductor device and method of building a pooled memory without using switchesPRIMEMAS INC·Filed 2025·Application pending·0 cites
- 0871US8443122B2Asynchronous upsizing circuit in data processing systemYUN JAEGEUN·Filed 2010·Granted May 14, 2013·4 cites·20 claims
- 0969US12373362B2Semiconductor device and method of building a pooled memory without using switchesPRIMEMAS INC·Filed 2024·Granted Jul 29, 2025·0 cites·11 claims
- 1066US8819322B2System on chip comprising interconnector and control method thereofYUN JAEGEUN·Filed 2012·Granted Aug 26, 2014·2 cites·13 claims
- 1161US8582709B2Bandwidth synchronization circuit and bandwidth synchronization methodYUN JAEGEUN·Filed 2010·Granted Nov 12, 2013·2 cites·29 claims
- 1252US9021171B2Bus system including a master device, a slave device, an interconnector coupled between the master device and the slave device, and an operating method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Apr 28, 2015·0 cites·20 claims
- 1345US2025045502A1Hub chiplet and hub chiplet packagePRIMEMAS INC·Filed 2024·Application pending·0 cites
- 1439US2012102250A1Bus systemYUN JAEGEUN·Filed 2011·Application pending·0 cites
- 1538US2012089758A1System On Chip Keeping Load Balance And Load Balancing Method ThereofYUN JAEGEUN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →