Inventor · disambiguated record
Jacson Liu
Also filed as: LIU JACSON
8 granted patents·1 pending application·67 citations·filing 1998–2005
86Inventor score
Top patents by PatentIndex Score
9 records- 0155US6319795B1Method for fabricating VLSI devices having trench isolation regionsMOSEL VITELIC INC·Filed 2000·Granted Nov 20, 2001·8 cites·19 claims
- 0244US6146997AMethod for forming self-aligned contact holeMOSEL VITELIC INC·Filed 1999·Granted Nov 14, 2000·12 cites·14 claims
- 0344US2005191822A1Shallow Trench Isolation Method for a Semiconductor WaferFiled 2005·Application pending·0 cites
- 0442US6218275B1Process for forming self-aligned contact of semiconductor deviceMOSEL VITELIC INC·Filed 1999·Granted Apr 17, 2001·11 cites·19 claims
- 0540US7045435B1Shallow trench isolation method for a semiconductor waferMOSEL VITELIC INC·Filed 1998·Granted May 16, 2006·8 cites·12 claims
- 0638US6346474B1Dual damascene processMOSEL VITELI INC·Filed 1999·Granted Feb 12, 2002·12 cites·20 claims
- 0736US6784115B1Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impuritiesMOSEL VITELIC INC·Filed 1998·Granted Aug 31, 2004·7 cites·22 claims
- 0834US6245467B1Patterned mask and a deep trench capacitor formed therebyMOSEL VITELIC INC·Filed 1999·Granted Jun 12, 2001·4 cites·16 claims
- 0933US6218267B1Shallow trench isolation method of a semiconductor waferMOSEL VITELIC INC·Filed 1998·Granted Apr 17, 2001·5 cites·5 claims
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