Inventor · disambiguated record
Frank S. Smith
Also filed as: SMITH FRANK S
9 granted patents·352 citations·filing 1990–1994
91Inventor score
Top patents by PatentIndex Score
9 records- 0183US5222244AMethod of modifying a microinstruction with operands specified by an instruction held in an alias registerINTEL CORP·Filed 1990·Granted Jun 22, 1993·109 cites·2 claims
- 0277US5185872ASystem for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busyINTEL CORP·Filed 1990·Granted Feb 9, 1993·79 cites·6 claims
- 0373USH1291HMicroprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructionsHINTON GLENN J·Filed 1990·Granted Feb 1, 1994·66 cites·10 claims
- 0451US5459845AInstruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completedINTEL CORP·Filed 1994·Granted Oct 17, 1995·26 cites·9 claims
- 0551US5023844ASix-way access ported RAM array cellINTEL CORP·Filed 1990·Granted Jun 11, 1991·15 cites·4 claims
- 0644US5313605AHigh bandwith output hierarchical memory store including a cache, fetch buffer and ROMINTEL CORP·Filed 1990·Granted May 17, 1994·17 cites·2 claims
- 0742US6378061B1Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuitINTEL CORP·Filed 1993·Granted Apr 23, 2002·14 cites·5 claims
- 0842US5428811AInterface between a register file which arbitrates between a number of single cycle and multiple cycle functional unitsINTEL CORP·Filed 1994·Granted Jun 27, 1995·14 cites·13 claims
- 0938US5454089ABranch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decodingINTEL CORP·Filed 1993·Granted Sep 26, 1995·12 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →