Inventor · disambiguated record
Prasad Chalasani
Also filed as: CHALASANI PRASAD · CHALASANI PRASAD H
24 granted patents·3 pending applications·101 citations·filing 1996–2022
94Inventor score
Top patents by PatentIndex Score
27 records- 0192US10467659B2Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platformMEDIAMATH INC·Filed 2017·Granted Nov 5, 2019·25 cites·20 claims
- 0290US11556964B2Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platformMEDIAMATH INC·Filed 2021·Granted Jan 17, 2023·2 cites·20 claims
- 0385US9467149B2Methods and systems for distributing clock and reset signals across an address macroKOOL CHIP INC·Filed 2014·Granted Oct 11, 2016·4 cites·14 claims
- 0484US9971975B2Optimal data eye for improved Vref marginINVECAS INC·Filed 2017·Granted May 15, 2018·7 cites·17 claims
- 0582US9564905B2Methods and systems for clocking a physical layer interfaceKOOL CHIP INC·Filed 2013·Granted Feb 7, 2017·4 cites·12 claims
- 0679US9715907B1Optimal data eye for improved Vref marginINVECAS INC·Filed 2016·Granted Jul 25, 2017·5 cites·10 claims
- 0779US6864732B2Flip-flop circuit with reduced power consumptionPROCKET NETWORKS INC·Filed 2002·Granted Mar 8, 2005·23 cites·11 claims
- 0878US10094859B1Voltage detectorINVECAS INC·Filed 2017·Granted Oct 9, 2018·2 cites·20 claims
- 0972US2024185304A1Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platformMEDIAMATH ACQUISITION CORP·Filed 2022·Application pending·0 cites
- 1069US10014866B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2017·Granted Jul 3, 2018·2 cites·19 claims
- 1168US11170413B1Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platformMEDIAMATH INC·Filed 2021·Granted Nov 9, 2021·0 cites·20 claims
- 1268US10505550B1Method and apparatus of operating synchronizing high-speed clock dividers to correct clock skewINVECAS INC·Filed 2019·Granted Dec 10, 2019·2 cites·20 claims
- 1367US11144937B2Framework for marketplace analysisVERIZON MEDIA INC·Filed 2018·Granted Oct 12, 2021·0 cites·19 claims
- 1464US9152920B2System and method of event publication in a goal achievement platformYAHOO INC·Filed 2013·Granted Oct 6, 2015·4 cites·33 claims
- 1560US9183564B2Framework for marketplace analysisBHATIA TARUN·Filed 2012·Granted Nov 10, 2015·0 cites·20 claims
- 1659US10037540B2Framework for marketplace analysisOATH INC·Filed 2015·Granted Jul 31, 2018·0 cites·17 claims
- 1758US5850150AFinal stage clock buffer in a clock distribution networkSUN MICROSYSTEMS INC·Filed 1996·Granted Dec 15, 1998·21 cites·27 claims
- 1856US10977697B2Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platformMEDIAMATH INC·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 1955US10502769B2Digital voltmeterINVECAS INC·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 2055US9948310B2Methods and systems for clocking a physical layer interfaceSOCTRONICS INC·Filed 2016·Granted Apr 17, 2018·0 cites·22 claims
- 2153US2014278929A1System and method identifying opportunities for advertising entities based on user goal achievementYAHOO INC·Filed 2013·Application pending·0 cites
- 2247US2014312945A1Delay Locked LoopIPPILI SHARAT·Filed 2013·Application pending·0 cites
- 2343US9954538B2Clock alignment scheme for data macros of DDR PHYINVECAS INC·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 2441US10361684B2Duty cycle detectionINVECAS INC·Filed 2017·Granted Jul 23, 2019·0 cites·10 claims
- 2541US8667133B2Methods and systems for determining the effect of a host on network latency while delivering online ADSFARAHAT AYMAN·Filed 2012·Granted Mar 4, 2014·0 cites·20 claims
- 2639US10791203B2Multi-protocol receiverSYNOPSYS INC·Filed 2017·Granted Sep 29, 2020·0 cites·19 claims
- 2738US9349421B2Memory interfaceKOOL CHIP INC·Filed 2014·Granted May 24, 2016·0 cites·14 claims
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