Inventor · disambiguated record
Charles R. Yount
Also filed as: YOUNT CHARLES · YOUNT CHARLES R
22 granted patents·8 pending applications·85 citations·filing 1999–2024
94Inventor score
Top patents by PatentIndex Score
30 records- 0192US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0289US10318291B2Providing vector horizontal compare functionality within a vector registerINTEL CORP·Filed 2017·Granted Jun 11, 2019·6 cites·19 claims
- 0388US9747101B2Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gatheringOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Aug 29, 2017·11 cites·30 claims
- 0488US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 0585US9804844B2Instruction and logic to provide stride-based vector load-op functionality with mask duplicationOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Oct 31, 2017·9 cites·30 claims
- 0685US9448794B2Instruction and logic to provide vector horizontal majority voting functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Sep 20, 2016·7 cites·27 claims
- 0784US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 0884US10248488B2Fault tolerance and detection by replication of input data and evaluating a packed data execution resultINTEL CORP·Filed 2015·Granted Apr 2, 2019·4 cites·13 claims
- 0982US9575757B2Efficient zero-based decompressionOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Feb 21, 2017·7 cites·15 claims
- 1081US10509726B2Instructions and logic for load-indices-and-prefetch-scatters operationsINTEL CORP·Filed 2015·Granted Dec 17, 2019·5 cites·20 claims
- 1180US9672036B2Instruction and logic to provide vector loads with strides and masking functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Jun 6, 2017·6 cites·30 claims
- 1276US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 1373US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 1473US9971391B2Method to assess energy efficiency of HPC system operated with and without power constraintsINTEL CORP·Filed 2015·Granted May 15, 2018·2 cites·22 claims
- 1568US10061746B2Instruction and logic for a vector format for processing computationsINTEL CORP·Filed 2014·Granted Aug 28, 2018·2 cites·20 claims
- 1666US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 1756US9928063B2Instruction and logic to provide vector horizontal majority voting functionalityINTEL CORP·Filed 2016·Granted Mar 27, 2018·0 cites·21 claims
- 1853US2017357514A1Instruction and logic to provide vector scatter-op and gather-op functionalityINTEL CORP·Filed 2017·Application pending·0 cites
- 1952US12032934B2Methods and apparatus to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write accessINTEL CORP·Filed 2021·Granted Jul 9, 2024·0 cites·25 claims
- 2051US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 2148US10241792B2Vector frequency expand instructionOULD AHMED VALL ELMOUSTAPHA·Filed 2011·Granted Mar 26, 2019·0 cites·21 claims
- 2247US10540177B2Efficient zero-based decompressionINTEL CORP·Filed 2017·Granted Jan 21, 2020·0 cites·15 claims
- 2346US9459866B2Vector frequency compress instructionOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Oct 4, 2016·0 cites·20 claims
- 2445US9665371B2Providing vector horizontal compare functionality within a vector registerOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted May 30, 2017·0 cites·22 claims
- 2544US6931629B1Method and apparatus for generation of validation testsINTEL CORP·Filed 1999·Granted Aug 16, 2005·16 cites·17 claims
- 2643US2005166096A1Method and apparatus for generation of validation testsFiled 2005·Application pending·0 cites
- 2741US2017269935A1Instruction and logic to provide vector loads and stores with strides and masking functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2017·Application pending·0 cites
- 2833US2017177360A1Instructions and Logic for Load-Indices-and-Scatter OperationsINTEL CORP·Filed 2015·Application pending·0 cites
- 2933US2017177349A1Instructions and Logic for Load-Indices-and-Prefetch-Gathers OperationsINTEL CORP·Filed 2015·Application pending·0 cites
- 3033US2017177363A1Instructions and Logic for Load-Indices-and-Gather OperationsINTEL CORP·Filed 2015·Application pending·0 cites
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