Inventor · disambiguated record
Sachin R. Sonkusale
Also filed as: SONKUSALE SACHIN R
16 granted patents·4 pending applications·106 citations·filing 2007–2016
92Inventor score
Files withMIE FUJITSU SEMICONDUCTOR LTD8SHIFREN LUCIAN4SUVOLTA INC3DSM SOLUTIONS INC2RANADE PUSHKAR2
Top patents by PatentIndex Score
20 records- 0197US8421162B2Advanced transistors with punch through suppressionSHIFREN LUCIAN·Filed 2010·Granted Apr 16, 2013·30 cites·8 claims
- 0295US9299801B1Method for fabricating a transistor device with a tuned dopant profileMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Mar 29, 2016·21 cites·14 claims
- 0394US8404551B2Source/drain extension control for advanced transistorsRANADE PUSHKAR·Filed 2010·Granted Mar 26, 2013·17 cites·11 claims
- 0491US8563384B2Source/drain extension control for advanced transistorsRANADE PUSHKAR·Filed 2013·Granted Oct 22, 2013·9 cites·20 claims
- 0586US8569128B2Semiconductor structure and method of fabrication thereof with mixed metal typesSHIFREN LUCIAN·Filed 2010·Granted Oct 29, 2013·8 cites·10 claims
- 0684US8530286B2Low power semiconductor transistor structure and method of fabrication thereofSHIFREN LUCIAN·Filed 2010·Granted Sep 10, 2013·6 cites·19 claims
- 0781US9577041B2Method for fabricating a transistor device with a tuned dopant profileMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Feb 21, 2017·2 cites·4 claims
- 0881US9041126B2Deeply depleted MOS transistors having a screening layer and methods thereofSUVOLTA INC·Filed 2013·Granted May 26, 2015·6 cites·19 claims
- 0979US9865596B2Low power semiconductor transistor structure and method of fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Jan 9, 2018·2 cites·14 claims
- 1079US8686511B2Source/drain extension control for advanced transistorsSUVOLTA INC·Filed 2013·Granted Apr 1, 2014·3 cites·20 claims
- 1173US9006843B2Source/drain extension control for advanced transistorsSUVOLTA INC·Filed 2014·Granted Apr 14, 2015·2 cites·20 claims
- 1257US10325986B2Advanced transistors with punch through suppressionMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Jun 18, 2019·0 cites·8 claims
- 1357US9893148B2Method for fabricating a transistor device with a tuned dopant profileMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Feb 13, 2018·0 cites·3 claims
- 1457US9508800B2Advanced transistors with punch through suppressionMIE FUJITSU SEMICONDUCTOR LTD·Filed 2015·Granted Nov 29, 2016·0 cites·18 claims
- 1557US9263523B2Advanced transistors with punch through suppressionMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Feb 16, 2016·0 cites·18 claims
- 1654US2013181298A1Advanced transistors with punch through suppressionSHIFREN LUCIAN·Filed 2013·Application pending·0 cites
- 1750US9224733B2Semiconductor structure and method of fabrication thereof with mixed metal typesMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Dec 29, 2015·0 cites·20 claims
- 1850US2009137088A1JFET Having a Step Channel Doping Profile and Method of FabricationDSM SOLUTIONS INC·Filed 2009·Application pending·0 cites
- 1947US2008272409A1JFET Having a Step Channel Doping Profile and Method of FabricationDSM SOLUTIONS INC·Filed 2007·Application pending·0 cites
- 2044US2008272394A1Junction field effect transistors in germanium and silicon-germanium alloys and method for making and usingKAPOOR ASHOK KUMAR·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →