Inventor · disambiguated record
Patrick E. Perry
Also filed as: PERRY PATRICK E · PERRY PATRICK EDWARD
17 granted patents·2 pending applications·594 citations·filing 1991–2015
95Inventor score
Top patents by PatentIndex Score
19 records- 0190US6477654B1Managing VT for reduced power using power setting commands in the instruction streamIBM·Filed 1999·Granted Nov 5, 2002·160 cites·32 claims
- 0285US6097243ADevice and method to reduce power consumption in integrated semiconductor devices using a low power groggy modeIBM·Filed 1998·Granted Aug 1, 2000·46 cites·34 claims
- 0384US6711719B2Method and apparatus for reducing power consumption in VLSI circuit designsIBM·Filed 2001·Granted Mar 23, 2004·41 cites·19 claims
- 0482US6479974B2Stacked voltage rails for low-voltage DC distributionIBM·Filed 2000·Granted Nov 12, 2002·33 cites·12 claims
- 0576US6026224ARedundant viasIBM·Filed 1996·Granted Feb 15, 2000·84 cites·16 claims
- 0674US6880074B2In-line code suppressionIBM·Filed 2000·Granted Apr 12, 2005·19 cites·10 claims
- 0773US5874833ATrue/complement output bus for reduced simulataneous switching noiseIBM·Filed 1997·Granted Feb 23, 1999·27 cites·20 claims
- 0868US6317840B1Control of multiple equivalent functional units for power reductionIBM·Filed 1999·Granted Nov 13, 2001·50 cites·16 claims
- 0967US9734920B2Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memoriesIBM·Filed 2015·Granted Aug 15, 2017·2 cites·17 claims
- 1060US6802033B1Low-power critical error rate communications controllerIBM·Filed 1999·Granted Oct 5, 2004·42 cites·17 claims
- 1159US5341310AWiring layout design method and system for integrated circuitsIBM·Filed 1991·Granted Aug 23, 1994·34 cites·19 claims
- 1257US5182468ACurrent limiting clamp circuitIBM·Filed 1991·Granted Jan 26, 1993·14 cites·3 claims
- 1349US6011383ALow powering apparatus for automatic reduction of power in active and standby modesIBM·Filed 1998·Granted Jan 4, 2000·19 cites·28 claims
- 1446US2008215237A1Design structure for adaptive route planning for gps-based navigationIBM·Filed 2008·Application pending·0 cites
- 1543US9224503B2Memory test with in-line error correction code logicIBM·Filed 2012·Granted Dec 29, 2015·0 cites·20 claims
- 1643US2007271034A1Adaptive route planning for gps-based navigationPERRY PATRICK E·Filed 2006·Application pending·0 cites
- 1742US6678847B1Real time function view system and methodIBM·Filed 1999·Granted Jan 13, 2004·9 cites·6 claims
- 1838US6269468B1Split I/O circuit for performance optimization of digital circuitsIBM·Filed 1999·Granted Jul 31, 2001·10 cites·16 claims
- 1932US5784575AOutput driver that parks output before going tristateIBM·Filed 1996·Granted Jul 21, 1998·4 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →