Inventor · disambiguated record
Kee-Wei Chung
Also filed as: CHUNG KEE-WEI
2 granted patents·7 pending applications·2 citations·filing 2010–2024
34Inventor score
Files withAP MEMORY TECH CORPORATION6CHUNG KEE WEI1POWERCHIP SEMICONDUCTOR MFG CORP1POWERTECH TECHNOLOGY INC1
Top patents by PatentIndex Score
9 records- 0158US2025116941A1Stitching method for exposure processPOWERCHIP SEMICONDUCTOR MFG CORP·Filed 2023·Application pending·0 cites
- 0255US8455984B2Integrated circuit structure and method of forming the sameCHUNG KEE WEI·Filed 2010·Granted Jun 4, 2013·2 cites·4 claims
- 0353US2024379623A1Semiconductor package structure and method for forming the sameAP MEMORY TECH CORPORATION·Filed 2024·Application pending·0 cites
- 0451US2025126811A1Semiconductor device and method of manufacturing thereofAP MEMORY TECH CORPORATION·Filed 2024·Application pending·0 cites
- 0551US2025279397A1Semiconductor structure and method for manufacturing a semiconductor structureAP MEMORY TECH CORPORATION·Filed 2024·Application pending·0 cites
- 0646US2025309203A1Semiconductor structure and manufacturing method thereofAP MEMORY TECH CORPORATION·Filed 2024·Application pending·0 cites
- 0746US2025125276A1Package substrate, semiconductor device, and method for forming package substrateAP MEMORY TECH CORPORATION·Filed 2024·Application pending·0 cites
- 0843US2024055343A1Semiconductor package structureAP MEMORY TECH CORPORATION·Filed 2023·Application pending·0 cites
- 0936US9972554B2Wafer level chip scale package having continuous through hole via configuration and fabrication method thereofPOWERTECH TECHNOLOGY INC·Filed 2017·Granted May 15, 2018·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →