Inventor · disambiguated record
Enric Musoll
Also filed as: MUSOLL ENRIC
15 granted patents·251 citations·filing 2000–2020
93Inventor score
Top patents by PatentIndex Score
15 records- 0192US7032226B1Methods and apparatus for managing a buffer of events in the backgroundMIPS TECH INC·Filed 2000·Granted Apr 18, 2006·69 cites·24 claims
- 0289US7035997B1Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processorsMIPS TECH INC·Filed 2000·Granted Apr 25, 2006·61 cites·24 claims
- 0387US7502876B1Background memory manager that determines if data structures fits in memory with memory state transactions mapMIPS TECH INC·Filed 2000·Granted Mar 10, 2009·49 cites·25 claims
- 0479US9256380B1Apparatus and method for packet memory datapath processing in high bandwidth packet processing devicesXPLIANT INC·Filed 2013·Granted Feb 9, 2016·5 cites·18 claims
- 0579US7058064B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2000·Granted Jun 6, 2006·23 cites·37 claims
- 0678US7715410B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2006·Granted May 11, 2010·6 cites·21 claims
- 0773US7661112B2Methods and apparatus for managing a buffer of events in the backgroundMIPS TECH INC·Filed 2006·Granted Feb 9, 2010·5 cites·28 claims
- 0873US7551626B2Queueing system for processors in packet routing operationsMIPS TECH INC·Filed 2006·Granted Jun 23, 2009·4 cites·40 claims
- 0973US7237093B1Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streamsMIPS TECH INC·Filed 2000·Granted Jun 26, 2007·20 cites·20 claims
- 1072US9736069B1Method for storing and retrieving packets in high bandwidth and low latency packet processing devicesXPLIANT INC·Filed 2013·Granted Aug 15, 2017·3 cites·10 claims
- 1171US9509585B1Apparatus and method for time stamping packets across several nodes in a networkXPLIANT INC·Filed 2013·Granted Nov 29, 2016·3 cites·12 claims
- 1271US9438539B1Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switchesXPLIANT INC·Filed 2013·Granted Sep 6, 2016·3 cites·7 claims
- 1352US9009364B1Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeedXPLIANT INC·Filed 2013·Granted Apr 14, 2015·0 cites·10 claims
- 1449US9262369B1Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeedXPLIANT INC·Filed 2015·Granted Feb 16, 2016·0 cites·5 claims
- 1545US11621923B2Queueing system with head-of-line block avoidanceMARVELL ASIA PTE LTD·Filed 2020·Granted Apr 4, 2023·0 cites·21 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →