Inventor · disambiguated record
Albert J. Van Norstrand, Jr.
Also filed as: VAN NORSTRAND ALBERT J · VAN NORSTRAND ALBERT J JR · VAN NORSTRAND ALBERT JAMES · VAN NORSTRAND JR ALBERT J
50 granted patents·9 pending applications·306 citations·filing 1992–2020
98Inventor score
Files withIBM54ABERNATHY CHRISTOPHER M1ABERNATHY CHRISTOPHER MICHAEL1DEMENT JONATHAN J1DOING RICHARD W1
Top patents by PatentIndex Score
59 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0296US9672043B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 6, 2017·29 cites·8 claims
- 0395US9690586B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 27, 2017·26 cites·4 claims
- 0495US9665372B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted May 30, 2017·25 cites·16 claims
- 0594US9690585B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted Jun 27, 2017·22 cites·9 claims
- 0693US10387686B2Hardware based isolation for secure execution of virtual machinesIBM·Filed 2017·Granted Aug 20, 2019·11 cites·24 claims
- 0792US9977678B2Reconfigurable parallel execution and load-store slice processorIBM·Filed 2015·Granted May 22, 2018·7 cites·10 claims
- 0891US10042647B2Managing a divided load reorder queueIBM·Filed 2016·Granted Aug 7, 2018·6 cites·20 claims
- 0990US9971602B2Reconfigurable processing method with modes controlling the partitioning of clusters and cache slicesIBM·Filed 2015·Granted May 15, 2018·6 cites·5 claims
- 1087US7313673B2Fine grained multi-thread dispatch block mechanismIBM·Filed 2005·Granted Dec 25, 2007·18 cites·20 claims
- 1186US10083039B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 1286US7437539B2Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 14, 2008·13 cites·10 claims
- 1384US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 1483US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 1582US10983800B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Apr 20, 2021·2 cites·20 claims
- 1682US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 1781US10157064B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2017·Granted Dec 18, 2018·2 cites·15 claims
- 1879US10409598B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Sep 10, 2019·1 cites·5 claims
- 1978US7434033B2Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 7, 2008·7 cites·11 claims
- 2077US9519502B2Virtual machine backupGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 13, 2016·3 cites·19 claims
- 2175US7818544B2Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock conditionIBM·Filed 2008·Granted Oct 19, 2010·5 cites·20 claims
- 2274US10067763B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2015·Granted Sep 4, 2018·1 cites·9 claims
- 2374US8082423B2Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updatesABERNATHY CHRISTOPHER MICHAEL·Filed 2005·Granted Dec 20, 2011·7 cites·1 claims
- 2472US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 2570US8200946B2Issue unit for placing a processor into a gradual slow mode of operationABERNATHY CHRISTOPHER M·Filed 2008·Granted Jun 12, 2012·4 cites·20 claims
- 2670US7605612B1Techniques for reducing power requirements of an integrated circuitIBM·Filed 2008·Granted Oct 20, 2009·6 cites·20 claims
- 2769US10545765B2Multi-level history buffer for transaction memory in a microprocessorIBM·Filed 2017·Granted Jan 28, 2020·1 cites·20 claims
- 2868US10884742B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Jan 5, 2021·0 cites·9 claims
- 2967US10831481B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
- 3064US10496406B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Dec 3, 2019·0 cites·9 claims
- 3164US8028151B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2008·Granted Sep 27, 2011·2 cites·13 claims
- 3264US6792524B1System and method cancelling a speculative branchIBM·Filed 1998·Granted Sep 14, 2004·48 cites·4 claims
- 3357US7953960B2Method and apparatus for delaying a load miss flush until issuing the dependent instructionIBM·Filed 2005·Granted May 31, 2011·1 cites·21 claims
- 3457US7496776B2Power throttling method and apparatusIBM·Filed 2003·Granted Feb 24, 2009·4 cites·9 claims
- 3556US10169046B2Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2017·Granted Jan 1, 2019·0 cites·12 claims
- 3656US2018260230A1Managing a divided load reorder queueIBM·Filed 2018·Application pending·0 cites
- 3755US11768684B2Compaction of architected registers in a simultaneous multithreading processorIBM·Filed 2020·Granted Sep 26, 2023·0 cites·17 claims
- 3855US8051315B2Power throttling apparatusIBM·Filed 2008·Granted Nov 1, 2011·0 cites·13 claims
- 3953US10248555B2Managing an effective address table in a multi-slice processorIBM·Filed 2016·Granted Apr 2, 2019·0 cites·13 claims
- 4053US10241905B2Managing an effective address table in a multi-slice processorIBM·Filed 2016·Granted Mar 26, 2019·0 cites·7 claims
- 4152US10552162B2Variable latency flush filteringIBM·Filed 2018·Granted Feb 4, 2020·0 cites·20 claims
- 4251US10909034B2Issue queue snooping for asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Feb 2, 2021·0 cites·20 claims
- 4351US2008201563A1Apparatus for Improving Single Thread Performance through Speculative ProcessingIBM·Filed 2008·Application pending·0 cites
- 4449US2010262813A1Detecting and Handling Short Forward Branch Conversion CandidatesIBM·Filed 2009·Application pending·0 cites
- 4549US2015378770A1Virtual machine backupIBM·Filed 2015·Application pending·0 cites
- 4648US7900027B2Scalable link stack control method with full support for speculative operationsIBM·Filed 2008·Granted Mar 1, 2011·0 cites·15 claims
- 4748US7475232B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2005·Granted Jan 6, 2009·0 cites·10 claims
- 4845US10831492B2Most favored branch issueIBM·Filed 2018·Granted Nov 10, 2020·0 cites·6 claims
- 4945US10528352B2Blocking instruction fetching in a computer processorIBM·Filed 2016·Granted Jan 7, 2020·0 cites·15 claims
- 5044US10387154B2Thread migration using a microcode engine of a multi-slice processorIBM·Filed 2016·Granted Aug 20, 2019·0 cites·20 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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