Inventor · disambiguated record
Mitchell G. Poplack
Also filed as: POPLACK MITCHELL · POPLACK MITCHELL G · POPLACK MITCHELL GRANT
65 granted patents·1 pending application·290 citations·filing 2004–2023
98Inventor score
Files withCADENCE DESIGN SYSTEMS INC50QUICKTURN DESIGN SYSTEMS INC9POPLACK MITCHELL3BERSHTEYN MIKHAIL2POPLACK MITCHELL G1
Top patents by PatentIndex Score
66 records- 0194US9379846B1System and method of encoding in a serializer/deserializerCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 28, 2016·25 cites·24 claims
- 0292US11308008B1Systems and methods for handling DPI messages outgoing from an emulator systemCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Apr 19, 2022·6 cites·20 claims
- 0391US10997343B1In-system scan test of chips in an emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·14 cites·20 claims
- 0491US10860763B1Data routing and multiplexing architecture to support serial links and advanced relocation of emulation modelsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 8, 2020·10 cites·30 claims
- 0591US9372947B1Compacting trace data generated by emulation processors during emulation of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 21, 2016·14 cites·20 claims
- 0689US11520531B1Systems and methods for intercycle gap refresh and backpressure managementCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Dec 6, 2022·3 cites·20 claims
- 0789US11042500B1Systems and methods for high-speed data transfer over a communication interfaceCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jun 22, 2021·6 cites·20 claims
- 0889US10198538B1Relocate targets to different domains in an emulatorCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 5, 2019·11 cites·17 claims
- 0988US7721036B2System and method for providing flexible signal routing and timingQUICKTURN DESIGN SYSTEMS INC·Filed 2005·Granted May 18, 2010·24 cites·35 claims
- 1087US9298866B1Method and system for modeling a flip-flop of a user designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 29, 2016·10 cites·20 claims
- 1186US10990728B1Functional built-in self-test architecture in an emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 27, 2021·4 cites·20 claims
- 1286US9697324B1System for concurrent target diagnostics fieldCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jul 4, 2017·3 cites·8 claims
- 1385US11176018B1Inline hardware compression subsystem for emulation trace dataCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Nov 16, 2021·7 cites·20 claims
- 1485US9647688B1System and method of encoding in a serializer/deserializerCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 9, 2017·9 cites·26 claims
- 1585US9171111B1Hardware emulation method and system using a port time shift registerCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 27, 2015·8 cites·18 claims
- 1684US11275598B1Dynamic one-bit multiplexing switch for emulation interconnectCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 15, 2022·4 cites·20 claims
- 1784US10324740B1Enhanced control system for flexible programmable logic and synchronizationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jun 18, 2019·4 cites·18 claims
- 1883US11194942B1Emulation system supporting four-state for sequential logic circuitsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Dec 7, 2021·3 cites·20 claims
- 1982US9702933B1System and method for concurrent interconnection diagnostics fieldCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jul 11, 2017·4 cites·23 claims
- 2081US10386909B1Method and system to mitigate large power load steps due to intermittent execution in a computation systemCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Aug 20, 2019·3 cites·18 claims
- 2180US11156660B1In-system scan test of electronic devicesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Oct 26, 2021·3 cites·20 claims
- 2280US9910810B1Multiphase I/O for processor-based emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 6, 2018·3 cites·18 claims
- 2379US9015026B2System and method incorporating an arithmetic logic unit for emulationPOPLACK MITCHELL·Filed 2010·Granted Apr 21, 2015·4 cites·39 claims
- 2478US11301414B1Systems and methods for communicating with clients with non-deterministic response delay over a communication interfaceCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 12, 2022·2 cites·20 claims
- 2578US11243856B1Framing protocol supporting low-latency serial interface in an emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Feb 8, 2022·2 cites·20 claims
- 2677US11900135B1Emulation system supporting representation of four-state signalsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Feb 13, 2024·2 cites·18 claims
- 2777US9292640B1Method and system for dynamic selection of a memory read portCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 22, 2016·6 cites·20 claims
- 2877US7904288B1Hardware emulator having a variable input emulation groupCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Mar 8, 2011·9 cites·16 claims
- 2977US7606698B1Method and apparatus for sharing data between discrete clusters of processorsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Oct 20, 2009·8 cites·15 claims
- 3076US8959010B1Emulation system with improved reliability of interconnect and a method for programming such interconnectBERSHTEYN MIKHAIL·Filed 2011·Granted Feb 17, 2015·5 cites·21 claims
- 3176US7739094B1Method and apparatus for designing an emulation chip using a selectable fastpath topologyCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·8 cites·18 claims
- 3275US10536553B1Method and system to transfer data between components of an emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 14, 2020·3 cites·18 claims
- 3375US8532975B2System and method implementing a simulation acceleration capture bufferPOPLACK MITCHELL·Filed 2010·Granted Sep 10, 2013·3 cites·18 claims
- 3474US7640155B2Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applicationsQUICKTURN DESIGN SYSTEMS INC·Filed 2005·Granted Dec 29, 2009·8 cites·21 claims
- 3572US11467620B1Architecture and methodology for tuning clock phases to minimize latency in a serial interfaceCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Oct 11, 2022·1 cites·20 claims
- 3672US11461522B1Emulation system supporting computation of four-state combinational functionsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Oct 4, 2022·1 cites·18 claims
- 3771US11106846B1Systems and methods for emulation data array compactionCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 31, 2021·1 cites·20 claims
- 3871US9904759B1System for concurrent target diagnostics fieldCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Feb 27, 2018·1 cites·9 claims
- 3971US9721048B1Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 1, 2017·2 cites·26 claims
- 4070US7440866B2System and method for validating an input/output voltage of a target systemQUICKTURN DESIGN SYSTEMS INC·Filed 2005·Granted Oct 21, 2008·6 cites·28 claims
- 4169US8160862B1Method and apparatus for controlling power in an emulation systemPOPLACK MITCHELL GRANT·Filed 2007·Granted Apr 17, 2012·7 cites·18 claims
- 4268US7555423B2Emulation processor interconnection architectureQUICKTURN DESIGN SYSTEMS INC·Filed 2005·Granted Jun 30, 2009·4 cites·10 claims
- 4367US7827023B2Method and apparatus for increasing the efficiency of an emulation engineCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Nov 2, 2010·4 cites·22 claims
- 4466US10509877B1Systems and methods for reducing latency when transferring I/O between an emulator and target deviceCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 17, 2019·1 cites·20 claims
- 4566US10303230B1Method and system to mitigate large power load steps due to intermittent execution in a computation systemCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 28, 2019·1 cites·19 claims
- 4666US10073795B1Data compression engine for I/O processing subsystemCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Sep 11, 2018·1 cites·20 claims
- 4766US7908465B1Hardware emulator having a selectable write-back processor unitCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Mar 15, 2011·3 cites·20 claims
- 4865US9069918B2System and method implementing full-rate writes for simulation accelerationPOPLACK MITCHELL·Filed 2010·Granted Jun 30, 2015·1 cites·20 claims
- 4965US8027828B2Method and apparatus for synchronizing processors in a hardware emulation systemCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 27, 2011·3 cites·15 claims
- 5063US12182485B1Embedded processor architecture with shared memory with design under testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Dec 31, 2024·1 cites·18 claims
Showing the top 50 of 66 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →