Inventor · disambiguated record
Sridhar H. Rangarajan
Also filed as: RANGARAJAN SRIDHAR · RANGARAJAN SRIDHAR H
23 granted patents·3 pending applications·59 citations·filing 2011–2019
92Inventor score
Top patents by PatentIndex Score
26 records- 0196US9501603B2Integrated circuit design changes using through-silicon viasIBM·Filed 2014·Granted Nov 22, 2016·40 cites·10 claims
- 0280US10223491B2Integrated circuit design changes using through-silicon viasIBM·Filed 2017·Granted Mar 5, 2019·2 cites·15 claims
- 0379US9569580B2Integrated circuit design changes using through-silicon viasIBM·Filed 2015·Granted Feb 14, 2017·2 cites·4 claims
- 0478US9659140B2Critical region identificationIBM·Filed 2015·Granted May 23, 2017·2 cites·6 claims
- 0577US10956644B2Integrated circuit design changes using through-silicon viasIBM·Filed 2019·Granted Mar 23, 2021·1 cites·20 claims
- 0677US8826208B1Computational thermal analysis during microchip designIBM·Filed 2013·Granted Sep 2, 2014·5 cites·20 claims
- 0775US10216885B2Adjusting scan connections based on scan control locationsIBM·Filed 2017·Granted Feb 26, 2019·1 cites·17 claims
- 0872US9378326B2Critical region identificationIBM·Filed 2014·Granted Jun 28, 2016·2 cites·3 claims
- 0968US10740177B2Optimizing error correcting code in three-dimensional stacked memoryIBM·Filed 2018·Granted Aug 11, 2020·2 cites·20 claims
- 1066US10168386B2Scan chain latency reductionIBM·Filed 2017·Granted Jan 1, 2019·1 cites·18 claims
- 1163US9412682B2Through-silicon via access device for integrated circuitsIBM·Filed 2014·Granted Aug 9, 2016·1 cites·11 claims
- 1255US10140414B2Critical region identificationIBM·Filed 2016·Granted Nov 27, 2018·0 cites·3 claims
- 1352US10725678B2Power management for memory subsystemsIBM·Filed 2018·Granted Jul 28, 2020·0 cites·20 claims
- 1451US9934348B2Adjusting scan connections based on scan control locationsIBM·Filed 2015·Granted Apr 3, 2018·0 cites·20 claims
- 1550US9087168B2Optimizing operating range of an electronic circuitIBM·Filed 2013·Granted Jul 21, 2015·0 cites·20 claims
- 1648US2018203066A1Scan chain latency reductionIBM·Filed 2017·Application pending·0 cites
- 1747US9633928B2Through-silicon via access device for integrated circuitsIBM·Filed 2015·Granted Apr 25, 2017·0 cites·6 claims
- 1847US2016117421A1Region-based synthesis of logic circuitsIBM·Filed 2014·Application pending·0 cites
- 1942US9557381B1Physically aware insertion of diagnostic circuit elementsIBM·Filed 2016·Granted Jan 31, 2017·0 cites·18 claims
- 2041US8495553B2Native threshold voltage switchingANTONY GEORGE·Filed 2011·Granted Jul 23, 2013·0 cites·20 claims
- 2141US2016117422A1Region-based synthesis of logic circuitsIBM·Filed 2015·Application pending·0 cites
- 2240US10534545B2Three-dimensional stacked memory optimizations for latency and powerIBM·Filed 2017·Granted Jan 14, 2020·0 cites·20 claims
- 2340US8572536B2Spare latch distributionANTONY GEORGE·Filed 2011·Granted Oct 29, 2013·0 cites·11 claims
- 2439US10318689B2Integrated circuit logic extraction using cloning and expansion for engineering change orderIBM·Filed 2017·Granted Jun 11, 2019·0 cites·17 claims
- 2537US10528288B2Three-dimensional stacked memory access optimizationIBM·Filed 2017·Granted Jan 7, 2020·0 cites·17 claims
- 2631US8638120B2Programmable gate array as drivers for data ports of spare latchesJAITLY ASHISH·Filed 2011·Granted Jan 28, 2014·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →