Inventor · disambiguated record
Sharad Vasantrao Chole
Also filed as: CHOLE SHARAD · Chole Sharad Vasantrao
7 granted patents·15 pending applications·9 citations·filing 2016–2025
75Inventor score
Top patents by PatentIndex Score
22 records- 0185US11151416B2Method and apparatus for efficiently processing convolution neural network operationsEXPEDERA INC·Filed 2019·Granted Oct 19, 2021·6 cites·20 claims
- 0283US12229589B2Method and apparatus for scheduling matrix operations in digital processing systemsEXPEDERA INC·Filed 2020·Granted Feb 18, 2025·2 cites·20 claims
- 0382US12008463B2Methods and apparatus for accessing external memory in a neural network processing systemEXPEDERA INC·Filed 2022·Granted Jun 11, 2024·1 cites·20 claims
- 0473US2024265234A1Digital Processing Circuits and Methods of Matrix Operations in an Artificially Intelligent EnvironmentEXPEDERA INC·Filed 2024·Application pending·0 cites
- 0565US12182717B2Feature extraction with a convolutional neural networkEXPEDERA INC·Filed 2021·Granted Dec 31, 2024·0 cites·12 claims
- 0663US2025045122A1Machine learning model scalability with distributed multi-layer processingEXPEDERA INC·Filed 2024·Application pending·0 cites
- 0762US2025045569A1Methods and Apparatus For Recomputing Neural NetworksEXPEDERA INC·Filed 2024·Application pending·0 cites
- 0859US2025068914A1Efficient tensor operations using slicingEXPEDERA INC·Filed 2024·Application pending·0 cites
- 0958US2025328562A1Systems and methods for heterogeneous large language model prompt attention-processingEXPEDERA INC·Filed 2025·Application pending·0 cites
- 1058US2024428046A1Methods And Apparatus For Managing Weight Data Accesses For Neural Network ProcessorsEXPEDERA INC·Filed 2023·Application pending·0 cites
- 1157US2025053614A1Systems and Processes for Data Reshape and Transport Using Matrix Processor CircuitsEXPEDERA INC·Filed 2024·Application pending·0 cites
- 1256US2024320496A1Methods and Apparatus For Packet Reorder Flow in a Neural Network Processing SystemEXPEDERA INC·Filed 2024·Application pending·0 cites
- 1355US2025061169A1Grid Sampling Methodologies in Neural Network Processor SystemsEXPEDERA INC·Filed 2023·Application pending·0 cites
- 1455US2025013259A1Methods and Devices for Clock Forwarding and RealignmentEXPEDERA INC·Filed 2024·Application pending·0 cites
- 1555US2025272145A1Systems and methods for heterogeneous large language model encoder and decoder processingEXPEDERA INC·Filed 2025·Application pending·0 cites
- 1653US11983616B2Methods and apparatus for constructing digital circuits for performing matrix operationsEXPEDERA INC·Filed 2018·Granted May 14, 2024·0 cites·10 claims
- 1751US2024427839A1Methods And Apparatus For Matrix Processing In A Neural Network Processing SystemEXPEDERA INC·Filed 2023·Application pending·0 cites
- 1850US2025131175A1Systems and Methods for Floating Point to Quantized Grid SamplingEXPEDERA INC·Filed 2023·Application pending·0 cites
- 1949US2024377853A1Power-Efficient Clocking and Clock ShapingEXPEDERA INC·Filed 2023·Application pending·0 cites
- 2048US2024152761A1Method and apparatus for using a packet architecture to process neural networks in a neural processing unitEXPEDERA INC·Filed 2022·Application pending·0 cites
- 2147US12141226B2Systems and processes for organizing and controlling multiple matrix processor circuitsEXPEDERA INC·Filed 2019·Granted Nov 12, 2024·0 cites·16 claims
- 2242US9965211B2Dynamic packet buffers with consolidation of low utilized memory banksCISCO TECH INC·Filed 2016·Granted May 8, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →