Inventor · disambiguated record
Ravi Kanth Kolan
Also filed as: KOLAN RAVI KANTH
13 granted patents·2 pending applications·261 citations·filing 2004–2015
93Inventor score
Technology areasH10W
Files withUNITED TEST & ASSEMBLY CT LT5TOH CHIN HOCK4UNITED TEST & ASSEMBLY CT LTD2KOLAN RAVI KANTH1LIU HAO1
Top patents by PatentIndex Score
15 records- 0197US9704726B2Packaging structural memberUTAC HEADQUARTERS PTE LTD·Filed 2015·Granted Jul 11, 2017·35 cites·19 claims
- 0297US9142487B2Packaging structural memberUNITED TEST & ASSEMBLY CT LT·Filed 2013·Granted Sep 22, 2015·44 cites·20 claims
- 0397US8426246B2Vented die and packageTOH CHIN HOCK·Filed 2012·Granted Apr 23, 2013·50 cites·21 claims
- 0496US8384203B2Packaging structural memberUNITED TEST & ASSEMBLY CT LT·Filed 2009·Granted Feb 26, 2013·50 cites·20 claims
- 0592US8115292B2Interposer for semiconductor packageTOH CHIN HOCK·Filed 2009·Granted Feb 14, 2012·37 cites·23 claims
- 0686US8143719B2Vented die and packageTOH CHIN HOCK·Filed 2008·Granted Mar 27, 2012·13 cites·29 claims
- 0778US8586465B2Through silicon via dies and packagesLIU HAO·Filed 2008·Granted Nov 19, 2013·7 cites·15 claims
- 0878US7883938B2Stacked die semiconductor package and method of assemblyUNITED TEST & ASSEMBLY CT LT·Filed 2008·Granted Feb 8, 2011·13 cites·7 claims
- 0975US8741762B2Through silicon via dies and packagesUNITED TEST & ASSEMBLY CT LT·Filed 2013·Granted Jun 3, 2014·3 cites·21 claims
- 1065US8772921B2Interposer for semiconductor packageTOH CHIN HOCK·Filed 2012·Granted Jul 8, 2014·2 cites·20 claims
- 1165US7830006B2Structurally-enhanced integrated circuit package and method of manufactureUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Nov 9, 2010·4 cites·10 claims
- 1264US8030761B2Mold design and semiconductor packageUNITED TEST & ASSEMBLY CT LT·Filed 2008·Granted Oct 4, 2011·2 cites·19 claims
- 1356US8399985B2Mold design and semiconductor packageKOLAN RAVI KANTH·Filed 2011·Granted Mar 19, 2013·1 cites·20 claims
- 1446US2010109169A1Semiconductor package and method of making the sameUNITED TEST & ASSEMBLY CT LTD·Filed 2009·Application pending·0 cites
- 1534US2008290509A1Chip Scale Package and Method of Assembling the SameUNITED TEST AND ASSEMBLY CT·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →