Inventor · disambiguated record
Chin Hock Toh
Also filed as: TOH CHIN H · TOH CHIN HOCK
19 granted patents·4 pending applications·305 citations·filing 2006–2016
95Inventor score
Files withTOH CHIN HOCK8UNITED TEST & ASSEMBLY CT LT6APPLIED MATERIALS INC3KOLAN RAVI KANTH1LIU HAO1
Top patents by PatentIndex Score
23 records- 0197US9704726B2Packaging structural memberUTAC HEADQUARTERS PTE LTD·Filed 2015·Granted Jul 11, 2017·35 cites·19 claims
- 0297US9142487B2Packaging structural memberUNITED TEST & ASSEMBLY CT LT·Filed 2013·Granted Sep 22, 2015·44 cites·20 claims
- 0397US8426246B2Vented die and packageTOH CHIN HOCK·Filed 2012·Granted Apr 23, 2013·50 cites·21 claims
- 0496US8384203B2Packaging structural memberUNITED TEST & ASSEMBLY CT LT·Filed 2009·Granted Feb 26, 2013·50 cites·20 claims
- 0594US7948095B2Semiconductor package and method of making the sameUNITED TEST & ASSEMBLY CT LT·Filed 2009·Granted May 24, 2011·45 cites·3 claims
- 0692US8115292B2Interposer for semiconductor packageTOH CHIN HOCK·Filed 2009·Granted Feb 14, 2012·37 cites·23 claims
- 0786US8143719B2Vented die and packageTOH CHIN HOCK·Filed 2008·Granted Mar 27, 2012·13 cites·29 claims
- 0878US8586465B2Through silicon via dies and packagesLIU HAO·Filed 2008·Granted Nov 19, 2013·7 cites·15 claims
- 0977US8647924B2Semiconductor package and method of packaging semiconductor devicesTOH CHIN HOCK·Filed 2010·Granted Feb 11, 2014·8 cites·23 claims
- 1075US8741762B2Through silicon via dies and packagesUNITED TEST & ASSEMBLY CT LT·Filed 2013·Granted Jun 3, 2014·3 cites·21 claims
- 1173US9117808B2Semiconductor packages and methods of packaging semiconductor devicesUNITED TEST & ASSEMBLY CT LT·Filed 2014·Granted Aug 25, 2015·3 cites·20 claims
- 1267US8703534B2Semiconductor packages and methods of packaging semiconductor devicesTOH CHIN HOCK·Filed 2012·Granted Apr 22, 2014·2 cites·20 claims
- 1365US9202801B2Thin substrate and mold compound handling using an electrostatic-chucking carrierTOH CHIN HOCK·Filed 2013·Granted Dec 1, 2015·2 cites·16 claims
- 1465US8772921B2Interposer for semiconductor packageTOH CHIN HOCK·Filed 2012·Granted Jul 8, 2014·2 cites·20 claims
- 1564US8030761B2Mold design and semiconductor packageUNITED TEST & ASSEMBLY CT LT·Filed 2008·Granted Oct 4, 2011·2 cites·19 claims
- 1662US9954051B2Structure and method of fabricating three-dimensional (3D) metal-insulator-metal (MIM) capacitor and resistor in semi-additive plating metal wiringSEE GUAN HUEI·Filed 2016·Granted Apr 24, 2018·1 cites·21 claims
- 1756US8399985B2Mold design and semiconductor packageKOLAN RAVI KANTH·Filed 2011·Granted Mar 19, 2013·1 cites·20 claims
- 1846US2010109169A1Semiconductor package and method of making the sameUNITED TEST & ASSEMBLY CT LTD·Filed 2009·Application pending·0 cites
- 1941US2014264954A1Passivation and warpage correction by nitride film for molded wafersAPPLIED MATERIALS INC·Filed 2014·Application pending·0 cites
- 2040US9219044B2Patterned photoresist to attach a carrier wafer to a silicon device waferTOH CHIN HOCK·Filed 2013·Granted Dec 22, 2015·0 cites·16 claims
- 2140US2014273354A1Fabrication of 3d chip stacks without carrier platesAPPLIED MATERIALS INC·Filed 2013·Application pending·0 cites
- 2239US10978334B2Sealing structure for workpiece to substrate bonding in a processing chamberAPPLIED MATERIALS INC·Filed 2015·Granted Apr 13, 2021·0 cites·18 claims
- 2332US2007210428A1Die stack system and methodTAN WOOI A·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →