Inventor · disambiguated record
Stacey G. Lloyd
Also filed as: LLOYD STACEY · LLOYD STACEY G
10 granted patents·297 citations·filing 1987–2003
91Inventor score
Files withIBM3INTEL CORP2PYRAMID TECHNOLOGY CORP2FUJITSU SIEMENS COMPUTERS LLC1INTERNAT BUSINESS MACHINES COM1
Top patents by PatentIndex Score
10 records- 0192US7124410B2Distributed allocation of system hardware resources for multiprocessor systemsIBM·Filed 2002·Granted Oct 17, 2006·95 cites·18 claims
- 0277US6785779B2Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architectureINTERNAT BUSINESS MACHINES COM·Filed 2002·Granted Aug 31, 2004·27 cites·27 claims
- 0369US4808855ADistributed precharge wire-or busINTEL CORP·Filed 1987·Granted Feb 28, 1989·18 cites·9 claims
- 0465US7406632B2Error reporting network in multiprocessor computerFUJITSU SIEMENS COMPUTERS LLC·Filed 2003·Granted Jul 29, 2008·15 cites·8 claims
- 0564US5787095AMultiprocessor computer backlane busPYRAMID TECHNOLOGY CORP·Filed 1997·Granted Jul 28, 1998·43 cites·4 claims
- 0661US4860322AAnti-clock skew distribution apparatusSIEMENS AG·Filed 1988·Granted Aug 22, 1989·30 cites·3 claims
- 0760US7093257B2Allocation of potentially needed resources prior to complete transaction receiptIBM·Filed 2002·Granted Aug 15, 2006·8 cites·32 claims
- 0858US4912631ABurst mode cache with wrap-around fillINTEL CORP·Filed 1987·Granted Mar 27, 1990·27 cites·2 claims
- 0957US5581713AMultiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitrationPYRAMID TECHNOLOGY CORP·Filed 1995·Granted Dec 3, 1996·33 cites·13 claims
- 1048US7237100B2Transaction redirection mechanism for handling late specification changes and design errorsIBM·Filed 2002·Granted Jun 26, 2007·1 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →