Inventor · disambiguated record
Richard J. Eickemeyer
Also filed as: EICKEMEYER JR RICHARD J · EICKEMEYER RICHARD J · EICKEMEYER RICHARD JAMES
68 granted patents·12 pending applications·2,948 citations·filing 1990–2022
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
80 records- 0197US6567839B1Thread switch control in a multithreaded processor systemIBM·Filed 1997·Granted May 20, 2003·424 cites·34 claims
- 0296US6694425B1Selective flush of shared and other pipeline stages in a multithread processorIBM·Filed 2000·Granted Feb 17, 2004·163 cites·15 claims
- 0395US7877580B2Branch lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Jan 25, 2011·41 cites·9 claims
- 0495US6931639B1Method for implementing a variable-partitioned queue for simultaneous multithreaded processorsIBM·Filed 2000·Granted Aug 16, 2005·115 cites·15 claims
- 0595US6697935B1Method and apparatus for selecting thread switch events in a multithreaded processorIBM·Filed 1997·Granted Feb 24, 2004·273 cites·21 claims
- 0695US6076157AMethod and apparatus to force a thread switch in a multithreaded processorIBM·Filed 1997·Granted Jun 13, 2000·292 cites·17 claims
- 0793US6061710AMultithreaded processor incorporating a thread latch register for interrupt service new pending threadsIBM·Filed 1997·Granted May 9, 2000·225 cites·3 claims
- 0891US10042647B2Managing a divided load reorder queueIBM·Filed 2016·Granted Aug 7, 2018·6 cites·20 claims
- 0991US6988186B2Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entryIBM·Filed 2001·Granted Jan 17, 2006·70 cites·12 claims
- 1091US5377336AImproved method to prefetch load instruction dataIBM·Filed 1992·Granted Dec 27, 1994·144 cites·2 claims
- 1190US7707396B2Data processing system, processor and method of data processing having improved branch target address cacheIBM·Filed 2006·Granted Apr 27, 2010·30 cites·21 claims
- 1290US5355460AIn-memory preprocessor for compounding a sequence of instructions for parallel computer system executionIBM·Filed 1993·Granted Oct 11, 1994·127 cites·26 claims
- 1389US6105051AApparatus and method to guarantee forward progress in execution of threads in a multithreaded processorIBM·Filed 1997·Granted Aug 15, 2000·148 cites·14 claims
- 1486US10078514B2Techniques for dynamic sequential instruction prefetchingIBM·Filed 2016·Granted Sep 18, 2018·4 cites·20 claims
- 1586US5500942AMethod of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructionsIBM·Filed 1995·Granted Mar 19, 1996·131 cites·24 claims
- 1685US7594096B2Load lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Sep 22, 2009·13 cites·20 claims
- 1784US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 1883US6088788ABackground completion of instruction and associated fetch request in a multithread processorIBM·Filed 1996·Granted Jul 11, 2000·123 cites·19 claims
- 1982US10209995B2Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructionsIBM·Filed 2014·Granted Feb 19, 2019·5 cites·17 claims
- 2082US7392366B2Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetchesIBM·Filed 2005·Granted Jun 24, 2008·9 cites·26 claims
- 2182US6049867AMethod and system for multi-thread switching only when a cache miss occurs at a second or higher levelIBM·Filed 1997·Granted Apr 11, 2000·110 cites·25 claims
- 2281US7844928B2Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent informationIBM·Filed 2008·Granted Nov 30, 2010·11 cites·20 claims
- 2379US10191847B2Prefetch performanceIBM·Filed 2017·Granted Jan 29, 2019·2 cites·20 claims
- 2476US9442736B2Techniques for selecting a predicted indirect branch address from global and local cachesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 13, 2016·4 cites·20 claims
- 2576US5651136ASystem and method for increasing cache efficiency through optimized data allocationIBM·Filed 1995·Granted Jul 22, 1997·91 cites·16 claims
- 2675US7421567B2Using a modified value GPR to enhance lookahead prefetchIBM·Filed 2004·Granted Sep 2, 2008·18 cites·10 claims
- 2774US9465744B2Data prefetch ramp implemenation based on memory utilizationIBM·Filed 2014·Granted Oct 11, 2016·3 cites·9 claims
- 2874US5459844APredecode instruction compoundingIBM·Filed 1994·Granted Oct 17, 1995·54 cites·11 claims
- 2973US10379857B2Dynamic sequential instruction prefetchingIBM·Filed 2018·Granted Aug 13, 2019·1 cites·20 claims
- 3073US5448746ASystem for comounding instructions in a byte stream prior to fetching and identifying the instructions for executionIBM·Filed 1994·Granted Sep 5, 1995·60 cites·50 claims
- 3172US10795683B2Predicting indirect branches using problem branch filtering and pattern cacheIBM·Filed 2014·Granted Oct 6, 2020·3 cites·8 claims
- 3271US7797521B2Method, system, and computer program product for path-correlated indirect address predictionsIBM·Filed 2007·Granted Sep 14, 2010·5 cites·19 claims
- 3371US5197135AMemory management for scalable compound instruction set machines with in-memory compoundingIBM·Filed 1990·Granted Mar 23, 1993·55 cites·15 claims
- 3469US10175987B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2016·Granted Jan 8, 2019·1 cites·18 claims
- 3569US7469407B2Method for resource balancing using dispatch flush in a simultaneous multithread processorIBM·Filed 2003·Granted Dec 23, 2008·13 cites·5 claims
- 3664US7620799B2Using a modified value GPR to enhance lookahead prefetchIBM·Filed 2008·Granted Nov 17, 2009·2 cites·14 claims
- 3762US10942743B2Splitting load hit store table for out-of-order processorIBM·Filed 2020·Granted Mar 9, 2021·0 cites·20 claims
- 3862US8347068B2Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessorIBM·Filed 2007·Granted Jan 1, 2013·2 cites·15 claims
- 3962US8261276B2Power-efficient thread priority enablementBOSE PRADIP·Filed 2008·Granted Sep 4, 2012·2 cites·16 claims
- 4061US8091073B2Scaling instruction intervals to identify collection points for representative instruction tracesBELL JR ROBERT H·Filed 2007·Granted Jan 3, 2012·2 cites·20 claims
- 4161US7444498B2Load lookahead prefetch for microprocessorsIBM·Filed 2004·Granted Oct 28, 2008·6 cites·19 claims
- 4261US6021481AEffective-to-real address cache managing apparatus and methodIBM·Filed 1997·Granted Feb 1, 2000·39 cites·11 claims
- 4360US10664279B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2019·Granted May 26, 2020·0 cites·18 claims
- 4458US11886883B2Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instructionIBM·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 4558US10725783B2Splitting load hit store table for out-of-order processorIBM·Filed 2018·Granted Jul 28, 2020·0 cites·20 claims
- 4657US10191845B2Prefetch performanceIBM·Filed 2017·Granted Jan 29, 2019·0 cites·7 claims
- 4757US5442767AAddress prediction to avoid address generation interlocks in computer systemsIBM·Filed 1992·Granted Aug 15, 1995·29 cites·8 claims
- 4856US8856453B2Persistent prefetch data stream settingsDALE JASON N·Filed 2012·Granted Oct 7, 2014·1 cites·20 claims
- 4956US8140829B2Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing executionEICKEMEYER RICHARD JAMES·Filed 2003·Granted Mar 20, 2012·7 cites·20 claims
- 5056US2018260230A1Managing a divided load reorder queueIBM·Filed 2018·Application pending·0 cites
Showing the top 50 of 80 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →