Inventor · disambiguated record
Tung-Chieh Chen
Also filed as: CHEN TUNG-CHIEH
17 granted patents·2 pending applications·68 citations·filing 2006–2017
92Inventor score
Top patents by PatentIndex Score
19 records- 0186US9256706B2Knowledge-based analog layout generatorSYNOPSYS TAIWAN CO LTD·Filed 2014·Granted Feb 9, 2016·10 cites·38 claims
- 0282US8607182B2Method of fast analog layout migrationCHEN TUNG-CHIEH·Filed 2012·Granted Dec 10, 2013·8 cites·5 claims
- 0379US7984410B2Hierarchy-based analytical placement method for an integrated circuitSPRINGSOFT USA INC·Filed 2008·Granted Jul 19, 2011·17 cites·16 claims
- 0478US8661388B2Method of packing-based macro placement and semiconductor chip using the sameCHEN TUNG-CHIEH·Filed 2009·Granted Feb 25, 2014·10 cites·13 claims
- 0575US11010528B2Knowledge-based analog layout generatorSYNOPSYS INC·Filed 2016·Granted May 18, 2021·2 cites·36 claims
- 0674US8407647B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioCHANG FONG-YUAN·Filed 2010·Granted Mar 26, 2013·3 cites·12 claims
- 0772US8875081B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioSYNOPSYS TAIWAN CO LTD·Filed 2013·Granted Oct 28, 2014·2 cites·10 claims
- 0872US8296708B1Method of constraint-hierarchy-driven IC placementCHEN TUNG-CHIEH·Filed 2012·Granted Oct 23, 2012·4 cites·18 claims
- 0972US7603640B2Multilevel IC floorplannerSPRINGSOFT INC·Filed 2006·Granted Oct 13, 2009·6 cites·30 claims
- 1065US8261223B2Hierarchy-based analytical placement method capable of macro rotation within an integrated circuitHSU MENG-KAI·Filed 2011·Granted Sep 4, 2012·3 cites·20 claims
- 1163US10719653B2Spine routing and pin grouping with multiple main spinesSYNOPSYS INC·Filed 2017·Granted Jul 21, 2020·1 cites·18 claims
- 1260US9747406B2Spine routing with multiple main spinesSYNOPSYS INC·Filed 2014·Granted Aug 29, 2017·1 cites·18 claims
- 1358US9665679B2Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratiosSYNOPSYS INC·Filed 2014·Granted May 30, 2017·0 cites·14 claims
- 1457US10409943B2Efficient analog layout prototyping by layout reuse with routing preservationSYNOPSYS INC·Filed 2014·Granted Sep 10, 2019·1 cites·42 claims
- 1553US9286433B2Method of fast analog layout migrationSYNOPSYS TAIWAN CO LTD·Filed 2013·Granted Mar 15, 2016·0 cites·40 claims
- 1652US9311441B2Switch cellSYNOPSYS TAIWAN CO LTD·Filed 2014·Granted Apr 12, 2016·0 cites·17 claims
- 1746US2007157146A1Method of packing-based macro placement and semiconductor chip using the sameMEDIATEK INC·Filed 2006·Application pending·0 cites
- 1837US2012180014A1Method of context-sensitive, trans-reflexive incremental design rule checking and its applicationsFANG MIN-YI·Filed 2011·Application pending·0 cites
- 1933US8524409B2Flow regulator for fuel cellTSENG CHUNG-JEN·Filed 2010·Granted Sep 3, 2013·0 cites·4 claims
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