Inventor · disambiguated record
Arunangshu Kundu
Also filed as: KUNDU ARUNANGSHU
31 granted patents·2 pending applications·581 citations·filing 2000–2014
97Inventor score
Top patents by PatentIndex Score
33 records- 0198US6838902B1Synchronous first-in/first-out block memory for a field programmable gate arrayACTEL CORP·Filed 2003·Granted Jan 4, 2005·196 cites·6 claims
- 0294US6751723B1Field programmable gate array and microcontroller system-on-a-chipACTEL CORP·Filed 2000·Granted Jun 15, 2004·107 cites·5 claims
- 0389US6980028B1Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2005·Granted Dec 27, 2005·13 cites·1 claims
- 0489US6867615B1Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2003·Granted Mar 15, 2005·28 cites·20 claims
- 0587US6825690B1Clock tree network in a field programmable gate arrayACTEL CORP·Filed 2003·Granted Nov 30, 2004·29 cites·20 claims
- 0686US7102385B2Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2005·Granted Sep 5, 2006·11 cites·3 claims
- 0785US7375553B1Clock tree network in a field programmable gate arrayACTEL CORP·Filed 2006·Granted May 20, 2008·12 cites·10 claims
- 0885US6718477B1Delay locked loop for an FPGA architectureFiled 2000·Granted Apr 6, 2004·39 cites·4 claims
- 0983US7516303B2Field programmable gate array and microcontroller system-on-a-chipACTEL CORP·Filed 2005·Granted Apr 7, 2009·11 cites·10 claims
- 1080US7484113B1Delay locked loop for an FPGA architectureACTEL CORP·Filed 2006·Granted Jan 27, 2009·8 cites·6 claims
- 1178US7385420B1Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracksACTEL CORP·Filed 2006·Granted Jun 10, 2008·6 cites·13 claims
- 1277US7385419B1Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2007·Granted Jun 10, 2008·7 cites·5 claims
- 1377US7227380B2Synchronous first-in/first-out block memory for a field programmable gate arrayACTEL CORP·Filed 2005·Granted Jun 5, 2007·6 cites·6 claims
- 1476US7199609B1Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2006·Granted Apr 3, 2007·8 cites·8 claims
- 1576US7171575B1Delay locked loop for and FPGA architectureACTEL CORP·Filed 2005·Granted Jan 30, 2007·9 cites·7 claims
- 1676US6980027B2Synchronous first-in/first-out block memory for a field programmable gate arrayACTEL CORP·Filed 2004·Granted Dec 27, 2005·12 cites·1 claims
- 1773US7069419B2Field programmable gate array and microcontroller system-on-a-chipACTEL CORP·Filed 2004·Granted Jun 27, 2006·14 cites·1 claims
- 1871US7545168B2Clock tree network in a field programmable gate arrayACTEL CORP·Filed 2008·Granted Jun 9, 2009·5 cites·9 claims
- 1971US7049846B1Clock tree network in a field programmable gate arrayACTEL CORP·Filed 2004·Granted May 23, 2006·12 cites·8 claims
- 2070US7394289B2Synchronous first-in/first-out block memory for a field programmable gate arrayACTEL CORP·Filed 2007·Granted Jul 1, 2008·4 cites·7 claims
- 2168US7075334B1Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracksACTEL CORP·Filed 2005·Granted Jul 11, 2006·3 cites·3 claims
- 2268US6976185B1Delay locked loop for an FPGA architectureACTEL CORP·Filed 2003·Granted Dec 13, 2005·10 cites·12 claims
- 2367US6750674B1Carry chain for use between logic modules in a field programmable gate arrayACTEL CORP·Filed 2002·Granted Jun 15, 2004·16 cites·8 claims
- 2465US9147025B2Method for efficient FPGA packingMICROSEMI SOC CORP·Filed 2014·Granted Sep 29, 2015·2 cites·5 claims
- 2565US7886130B2Field programmable gate array and microcontroller system-on-a-chipACTEL CORP·Filed 2008·Granted Feb 8, 2011·2 cites·9 claims
- 2657US6891396B1Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracksACTEL CORP·Filed 2002·Granted May 10, 2005·6 cites·8 claims
- 2754US7941685B2Delay locked loop for an FPGA architectureACTEL CORP·Filed 2008·Granted May 10, 2011·0 cites·10 claims
- 2852US7579869B2Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracksACTEL CORP·Filed 2008·Granted Aug 25, 2009·0 cites·18 claims
- 2952US7126374B2Multi-level routing architecture in a field programmable gate array having transmitters and receiversACTEL CORP·Filed 2005·Granted Oct 24, 2006·1 cites·2 claims
- 3052US6946871B1Multi-level routing architecture in a field programmable gate array having transmitters and receiversACTEL CORP·Filed 2002·Granted Sep 20, 2005·4 cites·16 claims
- 3145US2008231319A1Dedicated input/output first in/first out module for a field programmable gate arrayACTEL CORP·Filed 2008·Application pending·0 cites
- 3245US2008218207A1Synchronous first-in/first-out block memory for a field programmable gate arrayACTEL CORP·Filed 2008·Application pending·0 cites
- 3344US7432733B1Multi-level routing architecture in a field programmable gate array having transmitters and receiversACTEL CORP·Filed 2006·Granted Oct 7, 2008·0 cites·14 claims
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