Inventor · disambiguated record
Cynthia Ann Edgeworth Allison
Also filed as: ALLISON CYNTHIA · ALLISON CYNTHIA ANN EDGEWORTH
16 granted patents·81 citations·filing 2010–2015
92Inventor score
Top patents by PatentIndex Score
16 records- 0198US8704826B1Primitive re-ordering between world-space and screen-space pipelines with buffer limited processingNVIDIA CORP·Filed 2013·Granted Apr 22, 2014·30 cites·20 claims
- 0291US8760460B1Hardware-managed virtual buffers using a shared memory for load distributionKILGARIFF EMMETT M·Filed 2010·Granted Jun 24, 2014·41 cites·23 claims
- 0380US9336002B2Data structures for efficient tiled renderingNVIDIA CORP·Filed 2013·Granted May 10, 2016·2 cites·20 claims
- 0479US10430989B2Multi-pass rendering in a screen space pipelineNVIDIA CORP·Filed 2015·Granted Oct 1, 2019·3 cites·18 claims
- 0575US9639366B2Techniques for managing graphics processing resources in a tile-based architectureNVIDIA CORP·Filed 2013·Granted May 2, 2017·1 cites·20 claims
- 0673US8917271B2Redistribution of generated geometric primitivesRHOADES JOHNNY S·Filed 2010·Granted Dec 23, 2014·4 cites·24 claims
- 0771US9792122B2Heuristics for improving performance in a tile based architectureNVIDIA CORP·Filed 2013·Granted Oct 17, 2017·0 cites·22 claims
- 0864US9483270B2Distributed tiled cachingNVIDIA CORP·Filed 2013·Granted Nov 1, 2016·0 cites·20 claims
- 0964US9448804B2Techniques for managing graphics processing resources in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Sep 20, 2016·0 cites·20 claims
- 1063US10083036B2Techniques for managing graphics processing resources in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Sep 25, 2018·0 cites·22 claims
- 1163US9542189B2Heuristics for improving performance in a tile-based architectureNVIDIA CORP·Filed 2013·Granted Jan 10, 2017·0 cites·20 claims
- 1262US10489875B2Data structures for efficient tiled renderingNVIDIA CORP·Filed 2013·Granted Nov 26, 2019·0 cites·20 claims
- 1362US9342311B2Techniques for adaptively generating bounding boxesNVIDIA CORP·Filed 2013·Granted May 17, 2016·0 cites·20 claims
- 1461US10282803B2State handling in a tiled architectureNVIDIA CORP·Filed 2013·Granted May 7, 2019·0 cites·25 claims
- 1548US10147222B2Multi-pass rendering in a screen space pipelineNVIDIA CORP·Filed 2015·Granted Dec 4, 2018·0 cites·20 claims
- 1645US10032243B2Distributed tiled cachingNVIDIA CORP·Filed 2013·Granted Jul 24, 2018·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →