Inventor · disambiguated record
Vadim Bassin
Also filed as: BASSIN VADIM
19 granted patents·1 pending application·202 citations·filing 2008–2021
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0195US8095824B2Performing mode switching in an unbounded transactional memory (UTM) systemGRAY JAN·Filed 2009·Granted Jan 10, 2012·82 cites·20 claims
- 0293US8886894B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2012·Granted Nov 11, 2014·15 cites·18 claims
- 0391US8250331B2Operating system virtual memory management for hardware transactional memoryYAMADA KOICHI·Filed 2009·Granted Aug 21, 2012·24 cites·7 claims
- 0486US8688951B2Operating system virtual memory management for hardware transactional memoryYAMADA KOICHI·Filed 2012·Granted Apr 1, 2014·8 cites·14 claims
- 0583US8365016B2Performing mode switching in an unbounded transactional memory (UTM) systemINTEL CORP·Filed 2011·Granted Jan 29, 2013·7 cites·20 claims
- 0683US8316194B2Mechanisms to accelerate transactions using buffered storesADL-TABATABAI ALI-REZA·Filed 2009·Granted Nov 20, 2012·8 cites·5 claims
- 0782US8688917B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2012·Granted Apr 1, 2014·6 cites·18 claims
- 0881US8806101B2Metaphysical address space for holding lossy metadata in hardwareSHEAFFER GAD·Filed 2008·Granted Aug 12, 2014·10 cites·12 claims
- 0980US9785462B2Registering a user-handler in hardware for transactional memory event handlingSHEAFFER GAD·Filed 2008·Granted Oct 10, 2017·10 cites·34 claims
- 1080US8627017B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·8 cites·25 claims
- 1177US8799582B2Extending cache coherency protocols to support locally buffered dataSHEAFFER GAD·Filed 2008·Granted Aug 5, 2014·8 cites·27 claims
- 1276US9195600B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2014·Granted Nov 24, 2015·2 cites·20 claims
- 1375US8769212B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2012·Granted Jul 1, 2014·3 cites·13 claims
- 1474US8356166B2Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriersMICROSOFT CORP·Filed 2009·Granted Jan 15, 2013·6 cites·15 claims
- 1568US8856466B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2012·Granted Oct 7, 2014·1 cites·19 claims
- 1668US8627014B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·3 cites·29 claims
- 1758US8489864B2Performing escape actions in transactionsSHEAFFER GAD·Filed 2009·Granted Jul 16, 2013·1 cites·20 claims
- 1855US9069670B2Mechanisms to accelerate transactions using buffered storesADL-TABATABAI ALI-REZA·Filed 2012·Granted Jun 30, 2015·0 cites·20 claims
- 1949US2010332768A1Flexible read- and write-monitored and buffered memory blocksMICROSOFT CORP·Filed 2009·Application pending·0 cites
- 2048US12455612B2Device, method and system to provide thread scheduling hints to a software processINTEL CORP·Filed 2021·Granted Oct 28, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →