Inventor · disambiguated record
James Arthur Farrell
Also filed as: FARRELL JAMES A · FARRELL JAMES ARTHUR
16 granted patents·2 pending applications·577 citations·filing 1990–2006
94Inventor score
Files withCOMPAQ COMPUTER CORP7HEWLETT PACKARD DEVELOPMENT CO4FREESCALE SEMICONDUCTOR INC2COMPAQ INFORMATION TECHNOLOGIE1DIGITAL EQUIPMENT CORP1
Top patents by PatentIndex Score
18 records- 0189US7100020B1Digital communications processorFREESCALE SEMICONDUCTOR INC·Filed 1999·Granted Aug 29, 2006·193 cites·9 claims
- 0288US5014195AConfigurable set associative cache with decoded data element enable linesDIGITAL EQUIPMENT CORP·Filed 1990·Granted May 7, 1991·140 cites·7 claims
- 0382US7647472B2High speed and high throughput digital communications processor with efficient cooperation between programmable processing componentsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 12, 2010·10 cites·6 claims
- 0475US6098166ASpeculative issue of instructions under a load miss shadowCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 1, 2000·73 cites·18 claims
- 0571US6675288B2Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·16 cites·16 claims
- 0662US6542987B1Method and circuits for early detection of a full queueHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Apr 1, 2003·31 cites·43 claims
- 0761US6167508ARegister scoreboard logic with register read availability signal to reduce instruction issue arbitration latencyCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 26, 2000·38 cites·22 claims
- 0849US6249855B1Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycleCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 19, 2001·21 cites·48 claims
- 0948US2005038979A1Method and circuits for early detection of a full queueFiled 2004·Application pending·0 cites
- 1047US8090930B2Method and circuits for early detection of a full queueFISCHER TIMOTHY CHARLES·Filed 2003·Granted Jan 3, 2012·2 cites·21 claims
- 1146US2004098566A1Method and apparatus for compacting a queueFiled 2003·Application pending·0 cites
- 1245US6122728ATechnique for ordering internal processor register accessesCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 19, 2000·19 cites·21 claims
- 1343US6704856B1Method for compacting an instruction queueHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Mar 9, 2004·14 cites·2 claims
- 1442US6877142B2Timing verifier for MOS devices and related methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 5, 2005·0 cites·18 claims
- 1540US6405304B1Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Jun 11, 2002·12 cites·8 claims
- 1629US6473888B1Timing verifier for MOS devices and related methodCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 29, 2002·4 cites·10 claims
- 1726US6658506B1Method and apparatus for performing timing verification of a circuitCOMPAQ COMPUTER CORP·Filed 1999·Granted Dec 2, 2003·4 cites·13 claims
- 1825US6438732B1Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)COMPAQ COMPUTER CORP·Filed 1999·Granted Aug 20, 2002·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →