Inventor · disambiguated record
Jennifer A. Navarro
Also filed as: NAVARRO JENNIFER · NAVARRO JENNIFER A · NAVARRO JENNIFER ALMORADIE
24 granted patents·1 pending application·288 citations·filing 1998–2019
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0187US8407701B2Facilitating quiesce operations within a logically partitioned computer systemGAERTNER UTE·Filed 2010·Granted Mar 26, 2013·14 cites·20 claims
- 0287US8140834B2System, method and computer program product for providing a programmable quiesce filtering registerHELLER LISA C·Filed 2008·Granted Mar 20, 2012·18 cites·18 claims
- 0383US7890700B2Method, system, and computer program product for cross-invalidation handling in a multi-level private cacheIBM·Filed 2008·Granted Feb 15, 2011·14 cites·11 claims
- 0481US6119219ASystem serialization with early release of individual processorIBM·Filed 1998·Granted Sep 12, 2000·98 cites·13 claims
- 0579US10025608B2Quiesce handling in multithreaded environmentsIBM·Filed 2014·Granted Jul 17, 2018·4 cites·8 claims
- 0677US8285941B2Enhancing timeliness of cache prefetchingEKANADHAM KATTAMURI·Filed 2008·Granted Oct 9, 2012·9 cites·14 claims
- 0776US6079013AMultiprocessor serialization with early release of processorsIBM·Filed 1998·Granted Jun 20, 2000·76 cites·11 claims
- 0869US7039762B2Parallel cache interleave accesses with address-sliced directoriesIBM·Filed 2003·Granted May 2, 2006·13 cites·20 claims
- 0968US7089408B2Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-executionIBM·Filed 2003·Granted Aug 8, 2006·14 cites·12 claims
- 1065US11036647B2Suspending translation look-aside buffer purge execution in a multi-processor environmentIBM·Filed 2019·Granted Jun 15, 2021·0 cites·16 claims
- 1164US10929312B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 1261US10698835B2Suspending translation look-aside buffer purge execution in a multi-processor environmentIBM·Filed 2017·Granted Jun 30, 2020·0 cites·12 claims
- 1361US10248575B2Suspending translation look-aside buffer purge execution in a multi-processor environmentIBM·Filed 2018·Granted Apr 2, 2019·0 cites·1 claims
- 1460US10353825B2Suspending translation look-aside buffer purge execution in a multi-processor environmentIBM·Filed 2017·Granted Jul 16, 2019·0 cites·8 claims
- 1560US10353828B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2017·Granted Jul 16, 2019·0 cites·7 claims
- 1659US10353827B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2017·Granted Jul 16, 2019·0 cites·13 claims
- 1759US9665424B2Recovery improvement for quiesced systemsIBM·Filed 2014·Granted May 30, 2017·0 cites·7 claims
- 1858US9678830B2Recovery improvement for quiesced systemsIBM·Filed 2014·Granted Jun 13, 2017·0 cites·14 claims
- 1957US10176002B2Quiesce handling in multithreaded environmentsIBM·Filed 2014·Granted Jan 8, 2019·0 cites·4 claims
- 2053US7035986B2System and method for simultaneous access of the same line in cache storageIBM·Filed 2003·Granted Apr 25, 2006·3 cites·18 claims
- 2149US8332614B2System, method and computer program product for providing a programmable quiesce filtering registerHELLER LISA C·Filed 2012·Granted Dec 11, 2012·0 cites·20 claims
- 2245US2008065834A1Method to Prevent Operand Data with No Locality from Polluting the Data CacheIBM·Filed 2006·Application pending·0 cites
- 2344US6035392AComputer with optimizing hardware for conditional hedge fetching into cache storageIBM·Filed 1998·Granted Mar 7, 2000·17 cites·7 claims
- 2432US6219758B1False exception for cancelled delayed requestsIBM·Filed 1998·Granted Apr 17, 2001·4 cites·8 claims
- 2532US6026488AMethod for conditional hedge fetching into cache storageIBM·Filed 1998·Granted Feb 15, 2000·4 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →