Inventor · disambiguated record
Chris A. Mccarty
Also filed as: MCCARTY CHRIS · MCCARTY CHRIS A
12 granted patents·1 pending application·141 citations·filing 1984–2013
90Inventor score
Top patents by PatentIndex Score
13 records- 0177US5547896ADirect etch for thin film resistor using a hard maskHARRIS CORP·Filed 1995·Granted Aug 20, 1996·53 cites·30 claims
- 0274US8274160B2Active area bonding compatible high current structuresGASNER JOHN T·Filed 2010·Granted Sep 25, 2012·3 cites·22 claims
- 0368US7795130B2Active area bonding compatible high current structuresINTERSIL INC·Filed 2007·Granted Sep 14, 2010·3 cites·11 claims
- 0467US7224074B2Active area bonding compatible high current structuresINTERSIL INC·Filed 2005·Granted May 29, 2007·3 cites·57 claims
- 0565US5270265AStress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structureHARRIS CORP·Filed 1992·Granted Dec 14, 1993·40 cites·12 claims
- 0660US7005369B2Active area bonding compatible high current structuresINTERSIL AMERICAN INC·Filed 2003·Granted Feb 28, 2006·8 cites·44 claims
- 0756US8946912B2Active area bonding compatible high current structuresINTERSIL INC·Filed 2013·Granted Feb 3, 2015·0 cites·15 claims
- 0854US8652960B2Active area bonding compatible high current structuresINTERSIL INC·Filed 2012·Granted Feb 18, 2014·0 cites·19 claims
- 0951US8569896B2Active area bonding compatible high current structuresGASNER JOHN T·Filed 2012·Granted Oct 29, 2013·0 cites·19 claims
- 1051US6441447B1Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for sameINTERSIL CORP·Filed 1998·Granted Aug 27, 2002·13 cites·15 claims
- 1149US4553315AN Contact compensation techniqueHARRIS CORP·Filed 1984·Granted Nov 19, 1985·10 cites·7 claims
- 1241US6350640B1CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistorINTERSIL INC·Filed 1994·Granted Feb 26, 2002·8 cites·21 claims
- 1334US2003006413A1Semiconductor test system and associated methods for wafer level acceptance testingUNIV FLORIDA·Filed 2002·Application pending·0 cites
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