Inventor · disambiguated record
Viswanathan Lakshmanan
Also filed as: LAKSHMANAN VISWANATHAN
17 granted patents·1 pending application·170 citations·filing 2000–2008
94Inventor score
Top patents by PatentIndex Score
18 records- 0177US8046726B2Waiver mechanism for physical verification of system designsLSI CORP·Filed 2008·Granted Oct 25, 2011·9 cites·20 claims
- 0276US6658630B1Method to translate UDPs using gate primitivesLSI LOGIC CORP·Filed 2000·Granted Dec 2, 2003·32 cites·36 claims
- 0374US7829973B2N cell height decoupling circuitLSI CORP·Filed 2007·Granted Nov 9, 2010·9 cites·20 claims
- 0472US7480878B2Method and system for layout versus schematic validation of integrated circuit designsLSI LOGIC CORPORTION·Filed 2005·Granted Jan 20, 2009·11 cites·10 claims
- 0572US7149989B2Method of early physical design validation and identification of texted metal short circuits in an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted Dec 12, 2006·21 cites·12 claims
- 0670US7107559B2Method of partitioning an integrated circuit design for physical design verificationLSI LOGIC CORP·Filed 2003·Granted Sep 12, 2006·17 cites·12 claims
- 0768US7007248B2Method and apparatus for implementing engineering change ordersLSI LOGIC CORP·Filed 2003·Granted Feb 28, 2006·17 cites·19 claims
- 0866US7231626B2Method of implementing an engineering change order in an integrated circuit design by windowsLSI CORP·Filed 2004·Granted Jun 12, 2007·15 cites·8 claims
- 0958US6668359B1Verilog to vital translatorLSI LOGIC CORP·Filed 2001·Granted Dec 23, 2003·8 cites·12 claims
- 1057US7219317B2Method and computer program for verifying an incremental change to an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted May 15, 2007·6 cites·20 claims
- 1156US7260803B2Incremental dummy metal insertionsLSI CORP·Filed 2003·Granted Aug 21, 2007·7 cites·22 claims
- 1256US6775811B2Chip design method for designing integrated circuit chips with embedded memoriesLSI LOGIC CORP·Filed 2002·Granted Aug 10, 2004·5 cites·15 claims
- 1353US6453451B1Generating standard delay format files with conditional path delay for designing integrated circuitsLSI LOGIC CORP·Filed 2001·Granted Sep 17, 2002·4 cites·14 claims
- 1452US7302654B2Method of automating place and route corrections for an integrated circuit design from physical design validationLSI CORP·Filed 2004·Granted Nov 27, 2007·3 cites·8 claims
- 1549US7853901B2Unified layer stack architectureLSI CORP·Filed 2008·Granted Dec 14, 2010·0 cites·20 claims
- 1647US7051318B1Web based OLA memory generatorLSI LOGIC CORP·Filed 2001·Granted May 23, 2006·4 cites·20 claims
- 1744US6691288B1Method to debug IKOS methodLSI LOGIC CORP·Filed 2001·Granted Feb 10, 2004·2 cites·18 claims
- 1844US2006090144A1Method of automating place and route corrections for an integrated circuit design from physical design validationLSI LOGIC CORP·Filed 2004·Application pending·0 cites
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