Inventor · disambiguated record
Frank Swiatowiec
Also filed as: SWIATOWIEC FRANK · SWIATOWIEC FRANK J · SWIATOWIEC FRANK JOHN
10 granted patents·4 pending applications·359 citations·filing 1974–2013
91Inventor score
Files withNANONEXUS INC4INNOCONNEX INC2MOTOROLA INC2VERIGY PTE LTD SINGAPORE2ADVANTEST SINGAPORE PTE LTD1
Top patents by PatentIndex Score
14 records- 0197US6917525B2Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springsNANONEXUS INC·Filed 2002·Granted Jul 12, 2005·180 cites·67 claims
- 0293US7382142B2High density interconnect system having rapid fabrication cycleNANONEXUS INC·Filed 2005·Granted Jun 3, 2008·43 cites·29 claims
- 0391US7872482B2High density interconnect system having rapid fabrication cycleVERIGY PTE LTD SINGAPORE·Filed 2007·Granted Jan 18, 2011·21 cites·24 claims
- 0488US8531202B2Probe card test apparatus and methodMOK SAMMY·Filed 2008·Granted Sep 10, 2013·23 cites·25 claims
- 0587US7876087B2Probe card repair using coupons with spring contacts and separate atachment pointsINNOCONNEX INC·Filed 2007·Granted Jan 25, 2011·14 cites·31 claims
- 0686US7126220B2Miniaturized contact springNANONEXUS INC·Filed 2003·Granted Oct 24, 2006·40 cites·25 claims
- 0770US7137830B2Miniaturized contact springNANONEXUS INC·Filed 2003·Granted Nov 21, 2006·14 cites·30 claims
- 0861US7884634B2High density interconnect system having rapid fabrication cycleVERIGY PTE LTD SINGAPORE·Filed 2009·Granted Feb 8, 2011·2 cites·8 claims
- 0953US2009090617A1Method and Apparatus for Producing Controlled Stresses and Stress Gradients in Sputtered FilmsGIAUQUE PIERRE H·Filed 2006·Application pending·0 cites
- 1051US4122527AEmitter coupled multiplier arrayMOTOROLA INC·Filed 1977·Granted Oct 24, 1978·14 cites·5 claims
- 1150US3942033ACurrent mode logic circuitMOTOROLA INC·Filed 1974·Granted Mar 2, 1976·8 cites·6 claims
- 1250US2013186746A1Method and Apparatus for Producing Controlled Stresses and Stress Gradients in Sputtered FilmsADVANTEST SINGAPORE PTE LTD·Filed 2013·Application pending·0 cites
- 1341US2005068054A1Standardized layout patterns and routing structures for integrated circuit wafer probe card assembliesFiled 2004·Application pending·0 cites
- 1440US2009064498A1Membrane spring fabrication processINNOCONNEX INC·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →