Inventor · disambiguated record
Roger L. Gilbertson
Also filed as: GILBERTSON ROGER L · GILBERTSON ROGER LEE
13 granted patents·945 citations·filing 1995–2000
95Inventor score
Files withUNISYS CORP13
Top patents by PatentIndex Score
13 records- 0192US6594785B1System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitionsUNISYS CORP·Filed 2000·Granted Jul 15, 2003·146 cites·33 claims
- 0289US6381715B1System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory moduleUNISYS CORP·Filed 1998·Granted Apr 30, 2002·83 cites·27 claims
- 0388US6240458B1System and method for programmably controlling data transfer request rates between data sources and destinations in a data processing systemUNISYS CORP·Filed 1998·Granted May 29, 2001·151 cites·33 claims
- 0481US6178466B1System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same.UNISYS CORP·Filed 1998·Granted Jan 23, 2001·102 cites·30 claims
- 0573US6295553B1Method and apparatus for prioritizing delivery of data transfer requestsUNISYS CORP·Filed 1998·Granted Sep 25, 2001·71 cites·16 claims
- 0671US6356991B1Programmable address translation systemUNISYS CORP·Filed 1997·Granted Mar 12, 2002·61 cites·27 claims
- 0771US6167489ASystem and method for bypassing supervisory memory intervention for data transfers between devices having local memoriesUNISYS CORP·Filed 1998·Granted Dec 26, 2000·61 cites·34 claims
- 0870US6182112B1Method of and apparatus for bandwidth control of transfers via a bi-directional interfaceUNISYS CORP·Filed 1998·Granted Jan 30, 2001·56 cites·46 claims
- 0970US5832304AMemory queue with adjustable priority and conflict detectionUNISYS CORP·Filed 1995·Granted Nov 3, 1998·64 cites·25 claims
- 1066US6457101B1System and method for providing the speculative return of cached data within a hierarchical memory systemUNISYS CORP·Filed 1999·Granted Sep 24, 2002·52 cites·20 claims
- 1161US6477620B1Cache-level return data by-pass system for a hierarchical memoryUNISYS CORP·Filed 1999·Granted Nov 5, 2002·41 cites·20 claims
- 1256US6260099B1Multi-level priority control system and method for managing concurrently pending data transfer requestsUNISYS CORP·Filed 1998·Granted Jul 10, 2001·33 cites·31 claims
- 1351US6510405B1Method and apparatus for selectively displaying signal values generated by a logic simulatorUNISYS CORP·Filed 1998·Granted Jan 21, 2003·24 cites·38 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →