Inventor · disambiguated record
Richard Schinella
Also filed as: SCHINELLA RICHARD · SCHINELLA RICHARD D
26 granted patents·2 pending applications·760 citations·filing 1975–2004
97Inventor score
Top patents by PatentIndex Score
28 records- 0194US6566262B1Method for creating self-aligned alloy capping layers for copper interconnect structuresLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·83 cites·23 claims
- 0293US6881664B2Process for planarizing upper surface of damascene wiring structure for integrated circuit structuresLSI LOGIC CORP·Filed 2003·Granted Apr 19, 2005·75 cites·16 claims
- 0391US6499003B2Method and apparatus for application of proximity correction with unitary segmentationLSI LOGIC CORP·Filed 1998·Granted Dec 24, 2002·88 cites·13 claims
- 0491US6350700B1Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structureLSI LOGIC CORP·Filed 2000·Granted Feb 26, 2002·59 cites·28 claims
- 0590US5663017AOptical corrective techniques with reticle formation and reticle stitching to provide design flexibilityLSI LOGIC CORP·Filed 1995·Granted Sep 2, 1997·78 cites·25 claims
- 0686US6503840B2Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoningLSI LOGIC CORP·Filed 2001·Granted Jan 7, 2003·40 cites·20 claims
- 0785US6730588B1Method of forming SiGe gate electrodeLSI LOGIC CORP·Filed 2001·Granted May 4, 2004·33 cites·18 claims
- 0881US6391795B1Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoningLSI LOGIC CORP·Filed 1999·Granted May 21, 2002·53 cites·14 claims
- 0979US6532585B1Method and apparatus for application of proximity correction with relative segmentationLSI LOGIC CORP·Filed 2000·Granted Mar 11, 2003·15 cites·35 claims
- 1074US5670425AProcess for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trenchLSI LOGIC CORP·Filed 1995·Granted Sep 23, 1997·41 cites·17 claims
- 1171US6800940B2Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoningLSI LOGIC CORP·Filed 2002·Granted Oct 5, 2004·12 cites·5 claims
- 1270US7020859B2Process skew results for integrated circuitsLSI LOGIC CORP·Filed 2003·Granted Mar 28, 2006·13 cites·19 claims
- 1370US6175953B1Method and apparatus for general systematic application of proximity correctionLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·29 cites·30 claims
- 1469US5895261AProcess for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trenchLSI LOGIC CORP·Filed 1997·Granted Apr 20, 1999·32 cites·7 claims
- 1564US6673498B1Method for reticle formation utilizing metal vaporizationLSI LOGIC CORP·Filed 2001·Granted Jan 6, 2004·7 cites·19 claims
- 1657US5652163AUse of reticle stitching to provide design flexibilityLSI LOGIC CORP·Filed 1994·Granted Jul 29, 1997·17 cites·7 claims
- 1757US5600182ABarrier metal technology for tungsten plug interconnectionLSI LOGIC CORP·Filed 1995·Granted Feb 4, 1997·20 cites·26 claims
- 1855US5827777AMethod of making a barrier metal technology for tungsten plug interconnectionLSI LOGIC CORP·Filed 1996·Granted Oct 27, 1998·18 cites·28 claims
- 1954US6174630B1Method of proximity correction with relative segmentationLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·12 cites·18 claims
- 2053US5674774AMethod of making self-aligned remote polysilicon contactsLSI LOGIC CORP·Filed 1995·Granted Oct 7, 1997·18 cites·16 claims
- 2152US3945857AMethod for fabricating double-diffused, lateral transistorsFAIRCHILD CAMERA INSTR CO·Filed 1975·Granted Mar 23, 1976·13 cites·3 claims
- 2251US6743474B1Method for growing thin filmsLSI LOGIC CORP·Filed 2001·Granted Jun 1, 2004·2 cites·12 claims
- 2347US6747358B1Self-aligned alloy capping layers for copper interconnect structuresLSI LOGIC CORP·Filed 2003·Granted Jun 8, 2004·2 cites·12 claims
- 2444US7081296B2Method for growing thin filmsLSI LOGIC CORP·Filed 2004·Granted Jul 25, 2006·0 cites·5 claims
- 2537US2003084587A1Substrate processing systemLSI LOGIC CORP·Filed 2002·Application pending·0 cites
- 2635US6518193B1Substrate processing systemLSI LOGIC CORP·Filed 2001·Granted Feb 11, 2003·0 cites·6 claims
- 2735US6426286B1Interconnection system with lateral barrier layerLSI LOGIC CORP·Filed 2000·Granted Jul 30, 2002·0 cites·8 claims
- 2835US2002064713A1Strong phase shift mask substratesFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →