Inventor · disambiguated record
Margaret Martonosi
Also filed as: MARTONOSI MARGARET
8 granted patents·2 pending applications·347 citations·filing 1997–2014
90Inventor score
Top patents by PatentIndex Score
10 records- 0191US6745336B1System and method of operand value based processor optimization by detecting a condition of pre-determined number of bits and selectively disabling pre-determined bit-fields by clock gatingUNIV PRINCETON·Filed 2000·Granted Jun 1, 2004·80 cites·41 claims
- 0284US8880844B1Inter-core cooperative TLB prefetchersBHATTACHARJEE ABHISHEK·Filed 2010·Granted Nov 4, 2014·17 cites·6 claims
- 0382US7472302B2Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decayAGERE SYSTEMS INC·Filed 2005·Granted Dec 30, 2008·12 cites·26 claims
- 0477US6038392AImplementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardwareNEC USA INC·Filed 1998·Granted Mar 14, 2000·79 cites·12 claims
- 0575US6324673B1Method and apparatus for edge-endpoint-based VLSI design rule checkingUNIV PRINCETON·Filed 1999·Granted Nov 27, 2001·76 cites·51 claims
- 0667US9524232B2Inter-core cooperative TLB prefetchersUNIV PRINCETON·Filed 2014·Granted Dec 20, 2016·2 cites·31 claims
- 0762US6415430B1Method and apparatus for SAT solver architecture with very low synthesis and layout overheadNEC USA INC·Filed 1999·Granted Jul 2, 2002·42 cites·24 claims
- 0860US6247164B1Configurable hardware system implementing Boolean Satisfiability and method thereofNEC USA INC·Filed 1997·Granted Jun 12, 2001·39 cites·15 claims
- 0937US2003145241A1Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decayFiled 2002·Application pending·0 cites
- 1035US2014240327A1Fine-grained cpu-gpu synchronization using full/empty bitsUNIV PRINCETON·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →