Inventor · disambiguated record
Jonathan D. Combs
Also filed as: COMBS JONATHAN · COMBS JONATHAN D
31 granted patents·17 pending applications·138 citations·filing 2001–2023
95Inventor score
Top patents by PatentIndex Score
48 records- 0193US9465680B1Method and apparatus for processor performance monitoringINTEL CORP·Filed 2015·Granted Oct 11, 2016·17 cites·24 claims
- 0288US10331454B2System and method for load balancing in out-of-order clustered decodingINTEL CORP·Filed 2016·Granted Jun 25, 2019·6 cites·17 claims
- 0386US7552254B1Associating address space identifiers with active contextsINTEL CORP·Filed 2003·Granted Jun 23, 2009·46 cites·20 claims
- 0483US10067762B2Apparatuses, methods, and systems for memory disambiguationINTEL CORP·Filed 2016·Granted Sep 4, 2018·4 cites·24 claims
- 0582US8225046B2Method and apparatus for saving power by efficiently disabling ways for a set-associative cacheLICHT MARTIN·Filed 2006·Granted Jul 17, 2012·13 cites·28 claims
- 0680US12190157B2Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processorINTEL CORP·Filed 2020·Granted Jan 7, 2025·2 cites·24 claims
- 0778US9454371B2Micro-architecture for eliminating MOV operationsMADDURI VENKATESWARA·Filed 2012·Granted Sep 27, 2016·7 cites·25 claims
- 0877US9703566B2Sharing TLB mappings between contextsCOMBS JONATHAN D·Filed 2011·Granted Jul 11, 2017·5 cites·20 claims
- 0977US9367317B2Loop streaming detector for standard and complex instruction typesCOMBS JONATHAN D·Filed 2013·Granted Jun 14, 2016·5 cites·20 claims
- 1076US10417001B2Physical register table for eliminating move instructionsINTEL CORP·Filed 2012·Granted Sep 17, 2019·4 cites·15 claims
- 1175US9766999B2Monitoring performance of a processing device to manage non-precise eventsINTEL CORP·Filed 2014·Granted Sep 19, 2017·3 cites·20 claims
- 1273US11907712B2Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipelineINTEL CORP·Filed 2020·Granted Feb 20, 2024·1 cites·24 claims
- 1372US9098284B2Method and apparatus for saving power by efficiently disabling ways for a set-associative cacheINTEL CORP·Filed 2014·Granted Aug 4, 2015·2 cites·12 claims
- 1472US6557898B2Device, system and method for labeling three-dimensional objectsBIOANALYTICAL SYSTEMS INC·Filed 2001·Granted May 6, 2003·15 cites·48 claims
- 1568US8656108B2Method and apparatus for saving power by efficiently disabling ways for a set-associative cacheLICHT MARTIN·Filed 2012·Granted Feb 18, 2014·2 cites·24 claims
- 1668US2023092268A1Branch type logging in last branch registersINTEL CORP·Filed 2022·Application pending·0 cites
- 1761US9804852B2Conditional execution support for ISA instructions using prefixesCOMBS JONATHAN D·Filed 2011·Granted Oct 31, 2017·1 cites·18 claims
- 1860US12229034B2Device, system and method for identifying a source of latency in pipeline circuitryINTEL CORP·Filed 2020·Granted Feb 18, 2025·0 cites·14 claims
- 1960US9329865B2Context control and parameter passing within microcode based instruction routinesCOMBS JONATHAN D·Filed 2013·Granted May 3, 2016·1 cites·20 claims
- 2059US2020210178A1Branch type logging in last branch registersINTEL CORP·Filed 2020·Application pending·0 cites
- 2157US10365988B2Monitoring performance of a processing device to manage non-precise eventsINTEL CORP·Filed 2017·Granted Jul 30, 2019·0 cites·20 claims
- 2255US7783871B2Method to remove stale branch predictions for an instruction prior to execution within a microprocessorINTEL CORP·Filed 2003·Granted Aug 24, 2010·4 cites·13 claims
- 2355US2024354108A1Memory safety using tag checking instructions and islands of tags in line with bucketed dataINTEL CORP·Filed 2023·Application pending·0 cites
- 2455US2025110848A1Circuitry and methods for enhanced selection of performance monitoringINTEL CORP·Filed 2023·Application pending·0 cites
- 2554US10592244B2Branch type logging in last branch registersINTEL CORP·Filed 2017·Granted Mar 17, 2020·0 cites·18 claims
- 2654US10579492B2Device, system and method for identifying a source of latency in pipeline circuitryINTEL CORP·Filed 2017·Granted Mar 3, 2020·0 cites·19 claims
- 2754US2025028532A1Direct, unconditional jumpINTEL CORP·Filed 2023·Application pending·0 cites
- 2853US8904112B2Method and apparatus for saving power by efficiently disabling ways for a set-associative cacheINTEL CORP·Filed 2013·Granted Dec 2, 2014·0 cites·12 claims
- 2953US2025004764A1Support for less than 512-bit operand processingINTEL CORP·Filed 2023·Application pending·0 cites
- 3051US12423103B2Instruction decode cluster offliningINTEL CORP·Filed 2021·Granted Sep 23, 2025·0 cites·15 claims
- 3149US12288072B2Methods, systems, and apparatuses for precise last branch record event loggingINTEL CORP·Filed 2021·Granted Apr 29, 2025·0 cites·24 claims
- 3249US12254319B2Scalable toggle point control circuitry for a clustered decode pipelineINTEL CORP·Filed 2021·Granted Mar 18, 2025·0 cites·24 claims
- 3349US2024220260A1Prefix extensions for extended general purpose registers with optimization features for non-destructive destinations and flags suppressionAGRON JASON·Filed 2022·Application pending·0 cites
- 3447US12093694B2Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decodersINTEL CORP·Filed 2021·Granted Sep 17, 2024·0 cites·20 claims
- 3547US9811338B2Flag non-modification extension for ISA instructions using prefixesCOMBS JONATHAN D·Filed 2011·Granted Nov 7, 2017·0 cites·18 claims
- 3646US2023205527A1Conversion instructionsINTEL CORP·Filed 2021·Application pending·0 cites
- 3746US2024220253A1Methods, systems, and apparatuses for variable width unaligned fetch in a processorINTEL CORP·Filed 2022·Application pending·0 cites
- 3846US2023205522A1Conversion instructionsINTEL CORP·Filed 2021·Application pending·0 cites
- 3946US2023205521A1Conversion instructionsINTEL CORP·Filed 2021·Application pending·0 cites
- 4045US12353881B2Circuitry and methods for power efficient generation of length markers for a variable length instruction setINTEL CORP·Filed 2020·Granted Jul 8, 2025·0 cites·24 claims
- 4145US8832419B2Enhanced microcode address stack pointer manipulationCOMBS JONATHAN D·Filed 2010·Granted Sep 9, 2014·0 cites·20 claims
- 4244US2005071518A1Flag value renamingINTEL CORP·Filed 2003·Application pending·0 cites
- 4343US2023401067A1Concurrently fetching instructions for multiple decode clustersINTEL CORP·Filed 2022·Application pending·0 cites
- 4439US2018004512A1System and Method for Out-of-Order Clustered DecodingINTEL CORP·Filed 2016·Application pending·0 cites
- 4539US2012079255A1Indirect branch prediction based on branch target buffer hysteresisCOMBS JONATHAN D·Filed 2010·Application pending·0 cites
- 4638US2012079248A1Aliased Parameter Passing Between Microcode Callers and Microcode SubroutinesCOMBS JONATHAN D·Filed 2010·Application pending·0 cites
- 4737US2012079237A1Saving Values Corresponding to Parameters Passed Between Microcode Callers and Microcode Subroutines from Microcode Alias Locations to a Destination Storage LocationCOMBS JONATHAN D·Filed 2010·Application pending·0 cites
- 4833US8793469B2Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulationSUBRAMANIAM KAMESWAR·Filed 2010·Granted Jul 29, 2014·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →