Inventor · disambiguated record
E. Ajith Amerasekera
Also filed as: AMERASEKERA E AJITH
13 granted patents·405 citations·filing 1996–2002
94Inventor score
Files withTEXAS INSTRUMENTS INC13
Top patents by PatentIndex Score
13 records- 0191US6081002ALateral SCR structure for ESD protection in trench isolated technologiesTEXAS INSTRUMENTS INC·Filed 1998·Granted Jun 27, 2000·96 cites·19 claims
- 0289US6040968AEOS/ESD protection for high density integrated circuitsTEXAS INSTRUMENTS INC·Filed 1998·Granted Mar 21, 2000·82 cites·29 claims
- 0387US6143594AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 7, 2000·40 cites·5 claims
- 0481US5930094ACascoded-MOS ESD protection circuits for mixed voltage chipsTEXAS INSTRUMENTS INC·Filed 1998·Granted Jul 27, 1999·51 cites·5 claims
- 0579US6628493B1System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasingTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 30, 2003·22 cites·20 claims
- 0673US6530064B1Method and apparatus for predicting an operational lifetime of a transistorTEXAS INSTRUMENTS INC·Filed 2000·Granted Mar 4, 2003·20 cites·8 claims
- 0771US6137144AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 24, 2000·27 cites·6 claims
- 0861US5949094AESD protection for high density DRAMs using triple-well technologyTEXAS INSTRUMENTS INC·Filed 1997·Granted Sep 7, 1999·21 cites·12 claims
- 0959US6469353B1Integrated ESD protection circuit using a substrate triggered lateral NPNTEXAS INSTRUMENTS INC·Filed 1996·Granted Oct 22, 2002·18 cites·19 claims
- 1053US6433392B1Electrostatic discharge device and methodTEXAS INSTRUMENTS INC·Filed 1999·Granted Aug 13, 2002·12 cites·2 claims
- 1145US5804860AIntegrated lateral structure for ESD protection in CMOS/BiCMOS technologiesTEXAS INSTRUMENTS INC·Filed 1996·Granted Sep 8, 1998·10 cites·15 claims
- 1243US7456477B2Electrostatic discharge device and methodTEXAS INSTRUMENTS INC·Filed 2002·Granted Nov 25, 2008·1 cites·2 claims
- 1337US5793083AMethod for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivityTEXAS INSTRUMENTS INC·Filed 1996·Granted Aug 11, 1998·5 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →