Inventor · disambiguated record
Gregory Charles Baldwin
Also filed as: BALDWIN GREGORY C · BALDWIN GREGORY CHARLES
13 granted patents·1 pending application·88 citations·filing 1999–2016
88Inventor score
Top patents by PatentIndex Score
14 records- 0187US9054214B1Methodology of forming CMOS gates on the secondary axis using double-patterning techniqueTEXAS INSTRUMENTS INC·Filed 2014·Granted Jun 9, 2015·8 cites·19 claims
- 0287US6143594AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 7, 2000·40 cites·5 claims
- 0378US8748256B2Integrated circuit having silicide block resistorZHAO SONG·Filed 2012·Granted Jun 10, 2014·7 cites·11 claims
- 0471US6137144AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 24, 2000·27 cites·6 claims
- 0569US8669775B2Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devicesCHOI YOUN SUNG·Filed 2010·Granted Mar 11, 2014·3 cites·16 claims
- 0666US8664968B2On-die parametric test modules for in-line monitoring of context dependent effectsBALDWIN GREGORY CHARLES·Filed 2010·Granted Mar 4, 2014·2 cites·16 claims
- 0757US8513105B2Flexible integration of logic blocks with transistors of different threshold voltagesBALDWIN GREGORY CHARLES·Filed 2010·Granted Aug 20, 2013·1 cites·14 claims
- 0854US9496142B2Dummy gate placement methodology to enhance integrated circuit performanceTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 15, 2016·0 cites·17 claims
- 0951US9947765B2Dummy gate placement methodology to enhance integrated circuit performanceTEXAS INSTRUMENTS INC·Filed 2016·Granted Apr 17, 2018·0 cites·10 claims
- 1047US8791527B2Device layout in integrated circuits to reduce stress from embedded silicon—germaniumBALDWIN GREGORY CHARLES·Filed 2012·Granted Jul 29, 2014·0 cites·5 claims
- 1145US8183117B2Device layout in integrated circuits to reduce stress from embedded silicon-germaniumBALDWIN GREGORY CHARLES·Filed 2010·Granted May 22, 2012·0 cites·9 claims
- 1242US8438526B2Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictionsBALDWIN GREGORY CHARLES·Filed 2010·Granted May 7, 2013·0 cites·15 claims
- 1341US8595656B2Marker layer to facilitate mask build with interactive layersATON THOMAS J·Filed 2010·Granted Nov 26, 2013·0 cites·24 claims
- 1436US2012280324A1Sram structure and process with improved stabilityXIONG WEIZE·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →