Inventor · disambiguated record

Shao-Huan Wang

Also filed as: WANG SHAO-HUAN

30 granted patents·2 pending applications·86 citations·filing 2016–2025

96Inventor score

Technology areasH10W G06F H10D G03F H10P

Files withTAIWAN SEMICONDUCTOR MFG CO LTD32

Top patents by PatentIndex Score

32 records

0198US11449656B2Method of designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 20, 2022·5 cites·20 claims
0298US11275886B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 15, 2022·8 cites·20 claims
0396US11727185B2System for designing semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 15, 2023·2 cites·20 claims
0496US11681853B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 20, 2023·3 cites·20 claims
0595US12014131B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 18, 2024·2 cites·20 claims
0694US11030383B2Integrated device and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 8, 2021·4 cites·20 claims
0794US10990745B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Apr 27, 2021·7 cites·20 claims
0893US10868538B1Logic cell structure and integrated circuit with the logic cell structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 15, 2020·6 cites·20 claims
0992US10521545B2Placement constraint method for multiple patterning of cell-based chip designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 31, 2019·4 cites·20 claims
1090US11669669B2Circuit layouts and related methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 6, 2023·2 cites·20 claims
1190US10678991B2Integrated device and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 9, 2020·7 cites·20 claims
1290US10289794B2Layout for semiconductor device including via pillar structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 14, 2019·5 cites·20 claims
1390US10157840B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 18, 2018·5 cites·20 claims
1490US9977857B1Method and circuit for via pillar optimizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 22, 2018·8 cites·20 claims
1588US10396063B2Circuit with combined cells and method for manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Aug 27, 2019·7 cites·8 claims
1687US10741539B2Standard cells and variations thereof within a standard cell libraryTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 11, 2020·4 cites·18 claims
1786US2024387373A1Integrated Circuit Having a High Cell DensityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
1885US12400067B2Integrated circuit and method of forming same and a systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
1984US11855632B2Logic cell structure and integrated circuit with the logic cell structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 26, 2023·1 cites·20 claims
2083US10817643B2Method of designing semiconductor device and system for implementing the methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 27, 2020·2 cites·20 claims
2181US9996657B2Systems and methods for generating a multiple patterning lithography compliant integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jun 12, 2018·2 cites·18 claims
2280US12418294B2Logic cell structure and integrated circuit with the logic cell structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
2379US12087690B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 10, 2024·0 cites·20 claims
2479US11748542B2Systems and methods for integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 5, 2023·1 cites·19 claims
2576US12254260B2Systems and methods for integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 18, 2025·0 cites·20 claims
2676US2025209249A1Systems and methods for integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
2772US11437319B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 6, 2022·0 cites·20 claims
2869US10509887B2Must-join pin sign-off methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 17, 2019·1 cites·20 claims
2965US11182533B2Standard cells and variations thereof within a standard cell libraryTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 23, 2021·0 cites·20 claims
3064US11170149B2Placement constraint method for multiple patterning of cell-based chip designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Nov 9, 2021·0 cites·20 claims
3161US10804200B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Oct 13, 2020·0 cites·20 claims
3255US11704472B2Standard cells and variations thereof within a standard cell libraryTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jul 18, 2023·0 cites·21 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →