Inventor · disambiguated record
Charles D. Wait
Also filed as: WAIT CHARLES D · WAIT CHARLES DAVID
35 granted patents·5 pending applications·310 citations·filing 2005–2021
97Inventor score
Top patents by PatentIndex Score
40 records- 0196US9971713B2Multi-petascale highly efficient parallel supercomputerGLOBALFOUNDRIES INC·Filed 2015·Granted May 15, 2018·30 cites·14 claims
- 0296US9081501B2Multi-petascale highly efficient parallel supercomputerASAAD SAMEH·Filed 2011·Granted Jul 14, 2015·115 cites·41 claims
- 0393US7873816B2Pre-loading context states by inactive hardware thread in advance of context switchIBM·Filed 2008·Granted Jan 18, 2011·36 cites·21 claims
- 0489US10318435B2Ensuring forward progress for nested translations in a memory management unitIBM·Filed 2017·Granted Jun 11, 2019·6 cites·13 claims
- 0587US10042417B2Branch prediction with power usage prediction and controlIBM·Filed 2016·Granted Aug 7, 2018·4 cites·19 claims
- 0687US8291201B2Dynamic merging of pipeline stages in an execution pipeline to reduce power consumptionSCHWINN STEPHEN JOSEPH·Filed 2008·Granted Oct 16, 2012·21 cites·25 claims
- 0786US11422947B2Determining page size via page table cacheIBM·Filed 2020·Granted Aug 23, 2022·2 cites·20 claims
- 0886US10067556B2Branch prediction with power usage prediction and controlIBM·Filed 2015·Granted Sep 4, 2018·4 cites·19 claims
- 0986US8930432B2Floating point execution unit with fixed point functionalityHICKEY MARK J·Filed 2011·Granted Jan 6, 2015·10 cites·22 claims
- 1086US8412980B2Fault tolerant stability critical execution checking using redundant execution pipelinesHICKEY MARK J·Filed 2010·Granted Apr 2, 2013·9 cites·19 claims
- 1185US8707094B2Fault tolerant stability critical execution checking using redundant execution pipelinesIBM·Filed 2013·Granted Apr 22, 2014·7 cites·20 claims
- 1281US9223753B2Dynamic range adjusting floating point execution unitIBM·Filed 2013·Granted Dec 29, 2015·5 cites·21 claims
- 1380US8412760B2Dynamic range adjusting floating point execution unitHICKEY MARK J·Filed 2008·Granted Apr 2, 2013·9 cites·18 claims
- 1477US8880852B2Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different addressHICKEY MARK J·Filed 2011·Granted Nov 4, 2014·4 cites·25 claims
- 1576US9395804B2Branch prediction with power usage prediction and controlIBM·Filed 2013·Granted Jul 19, 2016·3 cites·20 claims
- 1675US8140830B2Structural power reduction in multithreaded processorSCHWINN STEPHEN JOSEPH·Filed 2008·Granted Mar 20, 2012·8 cites·24 claims
- 1775US7296108B2Apparatus and method for efficient transmission of unaligned dataIBM·Filed 2005·Granted Nov 13, 2007·7 cites·7 claims
- 1874US7975172B2Redundant execution of instructions in multistage execution pipeline during unused execution cyclesIBM·Filed 2008·Granted Jul 5, 2011·6 cites·19 claims
- 1974US7814299B2Designating operands with fewer bits in instruction code by indexing into destination register history table for each threadIBM·Filed 2008·Granted Oct 12, 2010·6 cites·1 claims
- 2072US9195463B2Processing core with speculative register preprocessing in unused execution unit cyclesHICKEY MARK J·Filed 2011·Granted Nov 24, 2015·3 cites·25 claims
- 2171US8629867B2Performing vector multiplicationHICKEY MARK J·Filed 2010·Granted Jan 14, 2014·3 cites·17 claims
- 2267US8255674B2Implied storage operation decode using redundant target address detectionHICKEY MARK JOSEPH·Filed 2009·Granted Aug 28, 2012·5 cites·20 claims
- 2366US8028153B2Data dependent instruction decodeIBM·Filed 2008·Granted Sep 27, 2011·3 cites·25 claims
- 2462US8560924B2Register file soft error recoveryFLEISCHER BRUCE M·Filed 2010·Granted Oct 15, 2013·1 cites·18 claims
- 2561US8522254B2Programmable integrated processor blocksHICKEY MARK J·Filed 2010·Granted Aug 27, 2013·1 cites·18 claims
- 2661US7752250B2Rounding floating point division resultsIBM·Filed 2006·Granted Jul 6, 2010·2 cites·1 claims
- 2758US10671537B2Reducing translation latency within a memory management unit using external caching structuresIBM·Filed 2017·Granted Jun 2, 2020·0 cites·13 claims
- 2858US10649902B2Reducing translation latency within a memory management unit using external caching structuresIBM·Filed 2017·Granted May 12, 2020·0 cites·7 claims
- 2955US11734188B2Unified translation miss queue for multiple address translation modesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·24 claims
- 3055US10380031B2Ensuring forward progress for nested translations in a memory management unitIBM·Filed 2017·Granted Aug 13, 2019·0 cites·7 claims
- 3154US2018300256A1Maintaining agent inclusivity within a distributed mmuIBM·Filed 2017·Application pending·0 cites
- 3253US2018300255A1Maintaining agent inclusivity within a distributed mmuIBM·Filed 2017·Application pending·0 cites
- 3352US11636043B2Sleeping and waking-up address translation that conflicts with translation level of active page table walksIBM·Filed 2021·Granted Apr 25, 2023·0 cites·20 claims
- 3452US11556475B2Power optimized prefetching in set-associative translation lookaside buffer structureIBM·Filed 2021·Granted Jan 17, 2023·0 cites·14 claims
- 3546US11221957B2Promotion of ERAT cache entriesIBM·Filed 2018·Granted Jan 11, 2022·0 cites·18 claims
- 3645US2009182986A1Processing Unit Incorporating Issue Rate-Based Predictive Thermal ManagementSCHWINN STEPHEN JOSEPH·Filed 2008·Application pending·0 cites
- 3744US10261793B2Instruction predication using instruction address pattern matchingHICKEY MARK J·Filed 2011·Granted Apr 16, 2019·0 cites·18 claims
- 3843US2007073933A1Asynchronous interface with vectored interface controlsIBM·Filed 2005·Application pending·0 cites
- 3942US2007006042A1Software debug support for cache flush with access to external data location(s) through debug portIBM·Filed 2005·Application pending·0 cites
- 4041US9075599B2Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bitsHICKEY MARK J·Filed 2010·Granted Jul 7, 2015·0 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →