Inventor · disambiguated record
Chong Ming Lin
Also filed as: LIN CHONG M · LIN CHONG-MING
43 granted patents·1,109 citations·filing 1989–2009
99Inventor score
Files withSEIKO EPSON CORP31QSPEED SEMICONDUCTOR INC4LOVOLTECH INC3DIGITAL EQUIPMENT CORP2LIN CHONG MING1
Top patents by PatentIndex Score
43 records- 0196US5452401ASelective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 1992·Granted Sep 19, 1995·167 cites·18 claims
- 0295US5655124ASelective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 1995·Granted Aug 5, 1997·153 cites·20 claims
- 0395US5444405AClock generator with programmable non-overlapping clock edge capabilitySEIKO EPSON CORP·Filed 1994·Granted Aug 22, 1995·55 cites·2 claims
- 0494US6430693B2Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 2001·Granted Aug 6, 2002·53 cites·20 claims
- 0587US6900682B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2003·Granted May 31, 2005·19 cites·10 claims
- 0686US7655964B1Programmable junction field effect transistor and method for programming sameQSPEED SEMICONDUCTOR INC·Filed 2005·Granted Feb 2, 2010·11 cites·11 claims
- 0786US7506185B2Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 2006·Granted Mar 17, 2009·8 cites·28 claims
- 0885US7220661B1Method of manufacturing a Schottky barrier rectifierQSPEED SEMICONDUCTOR INC·Filed 2004·Granted May 22, 2007·30 cites·22 claims
- 0985US6323711B2Clock generator with programmable non-overlapping-clock-edge-capabilitySEIKO EPSON CORP·Filed 2000·Granted Nov 27, 2001·18 cites·7 claims
- 1085US6256743B1Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 1998·Granted Jul 3, 2001·68 cites·8 claims
- 1184US7082543B2Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 2003·Granted Jul 25, 2006·21 cites·32 claims
- 1284US6163194AIntegrated circuit with hardware-based programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 1999·Granted Dec 19, 2000·26 cites·7 claims
- 1383US6774417B1Electrostatic discharge protection device for integrated circuitsLOVOLTECH INC·Filed 2002·Granted Aug 10, 2004·26 cites·16 claims
- 1483US5787297ASelective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 1997·Granted Jul 28, 1998·61 cites·12 claims
- 1580US6489826B2Clock generator with programmable non-overlapping clock-edge capabilitySEIKO EPSON CORP·Filed 2001·Granted Dec 3, 2002·13 cites·24 claims
- 1679US6587952B2Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 2002·Granted Jul 1, 2003·14 cites·13 claims
- 1777US8117468B2Selective power-down for high performance CPU/systemLIN CHONG MING·Filed 2009·Granted Feb 14, 2012·5 cites·34 claims
- 1877US6653881B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2002·Granted Nov 25, 2003·11 cites·14 claims
- 1975US7642832B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2008·Granted Jan 5, 2010·4 cites·11 claims
- 2072US7227242B1Structure and method for enhanced performance in semiconductor substratesQSPEED SEMICONDUCTOR INC·Filed 2003·Granted Jun 5, 2007·21 cites·6 claims
- 2172US7009229B1Electrostatic discharge protection device for integrated circuitsLOVOLTECH INC·Filed 2004·Granted Mar 7, 2006·14 cites·18 claims
- 2272US5581742AApparatus and method for emulating a microelectronic device by interconnecting and running test vectors on physically implemented functional modulesSEIKO EPSON CORP·Filed 1994·Granted Dec 3, 1996·51 cites·18 claims
- 2371US7075132B1Programmable junction field effect transistor and method for programming the sameLOVOLTECH INC·Filed 2002·Granted Jul 11, 2006·13 cites·10 claims
- 2470US7238976B1Schottky barrier rectifier and method of manufacturing the sameQSPEED SEMICONDUCTOR INC·Filed 2004·Granted Jul 3, 2007·12 cites·20 claims
- 2570US5966037AMethod for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP OF TOKYO JAPA·Filed 1997·Granted Oct 12, 1999·15 cites·4 claims
- 2669US6785761B2Selective power-down for high performance CPU/systemSEIKO EPSON CORP·Filed 2003·Granted Aug 31, 2004·7 cites·63 claims
- 2768US5017985AInput protection arrangement for VLSI integrated circuit devicesDIGITAL EQUIPMENT CORP·Filed 1989·Granted May 21, 1991·28 cites·6 claims
- 2867US5581562AIntegrated circuit device implemented using a plurality of partially defective integrated circuit chipsSEIKO EPSON CORP·Filed 1994·Granted Dec 3, 1996·40 cites·13 claims
- 2964US7352222B2Clock generator with programmable non-overlapping-clock-edge capabilitySEIKO EPSON CORP·Filed 2005·Granted Apr 1, 2008·2 cites·6 claims
- 3060US5630091AHigh density buffer architecture and methodSEIKO EPSON CORP·Filed 1994·Granted May 13, 1997·28 cites·13 claims
- 3159US5726904APower bus having power slits embodied therein and method for making the sameSEIKO EPSON CORP·Filed 1996·Granted Mar 10, 1998·13 cites·16 claims
- 3258US5909377AMethod for manufacturing a power bus on a chipSEIKO EPSON CORP·Filed 1997·Granted Jun 1, 1999·12 cites·11 claims
- 3357US5561789APower bus having power slits and holes embodied therein, and method for making the sameSEIKO EPSON CORP·Filed 1995·Granted Oct 1, 1996·11 cites·11 claims
- 3456US5345394AMethod for generating power slitsS MOS SYSTEMS INC·Filed 1992·Granted Sep 6, 1994·13 cites·13 claims
- 3554US4952994AInput protection arrangement for VLSI integrated circuit devicesDIGITAL EQUIPMENT CORP·Filed 1989·Granted Aug 28, 1990·16 cites·13 claims
- 3652US7516436B2Method for manufacturing a power bus on a chipSEIKO EPSON CORP·Filed 2006·Granted Apr 7, 2009·0 cites·15 claims
- 3751US6842885B2Computer program product for defining slits in a bus on a chipSEIKO EPSON CORP·Filed 2002·Granted Jan 11, 2005·2 cites·17 claims
- 3851US6378120B2Power bus and method for generating power slits thereinSEIKO EPSON CORP·Filed 2001·Granted Apr 23, 2002·2 cites·8 claims
- 3950US5600815AHigh density buffer memory architectureSEIKO EPSON CORP·Filed 1995·Granted Feb 4, 1997·19 cites·5 claims
- 4050US5461578AA power bus having power slits embodied thereinSEIKO EPSON CORP·Filed 1994·Granted Oct 24, 1995·9 cites·8 claims
- 4145US5806084ASpace saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memorySEIKO EPSON CORP·Filed 1997·Granted Sep 8, 1998·14 cites·11 claims
- 4244US7103867B2Method for manufacturing a power bus on a chipSEIKO EPSON CORP·Filed 2004·Granted Sep 5, 2006·0 cites·16 claims
- 4340US6233721B1Power bus and method for generating power slits thereinSEIKO EPSON CORP·Filed 1999·Granted May 15, 2001·4 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →