Inventor · disambiguated record
Vishwani D. Agrawal
Also filed as: AGRAWAL VISHWANI · AGRAWAL VISHWANI D · AGRAWAL VISHWANI DEO
13 granted patents·459 citations·filing 1982–2021
94Inventor score
Top patents by PatentIndex Score
13 records- 0193US5043986AMethod and integrated circuit adapted for partial scan testabilityAT & T BELL LAB·Filed 1989·Granted Aug 27, 1991·86 cites·11 claims
- 0290US4493077AScan testable integrated circuitAT & T LAB·Filed 1982·Granted Jan 8, 1985·92 cites·9 claims
- 0386US5606567ADelay testing of high-performance digital components by a slow-speed testerLUCENT TECHNOLOGIES INC·Filed 1994·Granted Feb 25, 1997·61 cites·23 claims
- 0478US5257268ACost-function directed search method for generating tests for sequential logic circuitsAT & T BELL LAB·Filed 1990·Granted Oct 26, 1993·41 cites·2 claims
- 0573US5499249AMethod and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)AT & T CORP·Filed 1994·Granted Mar 12, 1996·34 cites·6 claims
- 0673US5461573AVLSI circuits designed for testability and methods for producing themNEC USA INC·Filed 1993·Granted Oct 24, 1995·37 cites·10 claims
- 0765US5657240ATesting and removal of redundancies in VLSI circuits with non-boolean primitivesNEC USA INC·Filed 1995·Granted Aug 12, 1997·27 cites·2 claims
- 0860US5228040ATestable implementations of finite state machines and methods for producing themAT & T BELL LAB·Filed 1990·Granted Jul 13, 1993·21 cites·21 claims
- 0959US5590135ATesting a sequential circuitLUCENT TECHNOLOGIES INC·Filed 1991·Granted Dec 31, 1996·21 cites·1 claims
- 1051US5365528AMethod for testing delay faults in non-scan sequential circuitsAT & T BELL LAB·Filed 1992·Granted Nov 15, 1994·15 cites·8 claims
- 1147US12306247B2System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuitsUNIV AUBURN·Filed 2021·Granted May 20, 2025·0 cites·20 claims
- 1242US6131181AMethod and system for identifying tested path delay faultsUNIV RUTGERS·Filed 1997·Granted Oct 10, 2000·13 cites·24 claims
- 1339US5983007ALow power circuits through hazard pulse suppressionLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 9, 1999·11 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →