Inventor · disambiguated record
John A. Wishneusky
Also filed as: WISHNEUSKY JOHN · WISHNEUSKY JOHN A · WISHNEUSKY JOHN ANDREW
23 granted patents·2 pending applications·613 citations·filing 1978–2010
96Inventor score
Top patents by PatentIndex Score
25 records- 0197US7653757B1Method for using a multi-master multi-slave bus for power managementZILKER LABS INC·Filed 2005·Granted Jan 26, 2010·148 cites·42 claims
- 0295US7793005B1Power management system using a multi-master multi-slave bus and multi-function point-of-load regulatorsZILKER LABS INC·Filed 2006·Granted Sep 7, 2010·53 cites·18 claims
- 0395US7685320B1Autonomous sequencing and fault spreadingZILKER LABS INC·Filed 2006·Granted Mar 23, 2010·52 cites·21 claims
- 0491US7908402B2Integrated multi-function point-of-load regulator circuitZILKER LABS INC·Filed 2010·Granted Mar 15, 2011·11 cites·20 claims
- 0590US8452897B1Method for using a multi-master multi-slave bus for power managementFERNALD KENNETH W·Filed 2006·Granted May 28, 2013·24 cites·59 claims
- 0689US8239597B2Device-to-device communication bus for distributed power managementWISHNEUSKY JOHN A·Filed 2009·Granted Aug 7, 2012·38 cites·32 claims
- 0784US4254477AReconfigurable memory circuitMC DONNELL DOUGLAS CORP·Filed 1978·Granted Mar 3, 1981·25 cites·29 claims
- 0876US6901507B2Context schedulingINTEL CORP·Filed 2001·Granted May 31, 2005·19 cites·23 claims
- 0973US7426215B2Method and apparatus for scheduling packetsINTEL CORP·Filed 2004·Granted Sep 16, 2008·18 cites·36 claims
- 1070US5765023ADMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computerCIRRUS LOGIC INC·Filed 1995·Granted Jun 9, 1998·62 cites·32 claims
- 1169US4975828AMulti-channel data communications controllerCIRRUS LOGIC INC·Filed 1987·Granted Dec 4, 1990·41 cites·18 claims
- 1266US6963535B2MAC bus interfaceINTEL CORP·Filed 2000·Granted Nov 8, 2005·10 cites·22 claims
- 1366US5781799ADMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllersCIRRUS LOGIC INC·Filed 1995·Granted Jul 14, 1998·53 cites·36 claims
- 1459US7522620B2Method and apparatus for scheduling packetsINTEL CORP·Filed 2003·Granted Apr 21, 2009·6 cites·48 claims
- 1557US7007156B2Multiple coprocessor architecture to process a plurality of subtasks in parallelINTEL CORP·Filed 2000·Granted Feb 28, 2006·5 cites·22 claims
- 1657US6981113B2Storage registers for a processor pipelineINTEL CORP·Filed 2003·Granted Dec 27, 2005·5 cites·20 claims
- 1755US6874080B2Context processing by substantially simultaneously selecting address and instruction of different contextsINTEL CORP·Filed 2001·Granted Mar 29, 2005·4 cites·21 claims
- 1854US7415027B2Processing frame bitsINTEL CORP·Filed 2003·Granted Aug 19, 2008·3 cites·25 claims
- 1953US6826676B2Extending immediate operands across plural computer instructions with indication of how many instructions are used to store the immediate operandINTEL CORP·Filed 2001·Granted Nov 30, 2004·3 cites·23 claims
- 2048US2006026596A1Context schedulingINTEL CORP·Filed 2005·Application pending·0 cites
- 2147US5566352ARegister-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanismCIRRUS LOGIC INC·Filed 1993·Granted Oct 15, 1996·18 cites·25 claims
- 2246US5864716ATagged data compression for parallel port interfaceCIRRUS LOGIC INC·Filed 1996·Granted Jan 26, 1999·13 cites·20 claims
- 2344US7243214B2Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessaryINTEL CORP·Filed 2003·Granted Jul 10, 2007·0 cites·11 claims
- 2444US2005220115A1Method and apparatus for scheduling packetsROMANO DAVID·Filed 2004·Application pending·0 cites
- 2531US5588145AMethod and arrangement for clock adjustment using programmable period binary rate multiplierCIRRUS LOGIC INC·Filed 1995·Granted Dec 24, 1996·2 cites·51 claims
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