Inventor · disambiguated record
Narendra S. Khandekar
Also filed as: KHANDEKAR NARENDRA · KHANDEKAR NARENDRA S
21 granted patents·1 pending application·579 citations·filing 1995–2003
96Inventor score
Files withINTEL CORP21
Top patents by PatentIndex Score
22 records- 0196US6639820B1Memory buffer arrangementINTEL CORP·Filed 2002·Granted Oct 28, 2003·119 cites·27 claims
- 0295US6981089B2Memory bus termination with memory unit having termination controlINTEL CORP·Filed 2001·Granted Dec 27, 2005·111 cites·28 claims
- 0387US6832177B2Method of addressing individual memory devices on a memory moduleINTEL CORP·Filed 2002·Granted Dec 14, 2004·42 cites·32 claims
- 0487US6567904B1Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devicesINTEL CORP·Filed 1995·Granted May 20, 2003·74 cites·16 claims
- 0574US7353329B2Memory buffer device integrating refresh logicINTEL CORP·Filed 2003·Granted Apr 1, 2008·21 cites·31 claims
- 0668US6243768B1Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system busINTEL CORP·Filed 1998·Granted Jun 5, 2001·27 cites·18 claims
- 0767US7000133B2Method and apparatus for controlling power states in a memory device utilizing state informationINTEL CORP·Filed 2002·Granted Feb 14, 2006·12 cites·25 claims
- 0860US5715476AMethod and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logicINTEL CORP·Filed 1995·Granted Feb 3, 1998·39 cites·25 claims
- 0958US5926828AMethod and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system busINTEL CORP·Filed 1996·Granted Jul 20, 1999·19 cites·1 claims
- 1057US6976121B2Apparatus and method to track command signal occurrence for DRAM data transferINTEL CORP·Filed 2002·Granted Dec 13, 2005·5 cites·26 claims
- 1154US5873119AMethod for parallel processing of dram read request in a memory-cache controller systemINTEL CORP·Filed 1996·Granted Feb 16, 1999·15 cites·40 claims
- 1248US6829184B2Apparatus and method for encoding auto-prechargeINTEL CORP·Filed 2002·Granted Dec 7, 2004·5 cites·24 claims
- 1348US5802603AMethod and apparatus for asymmetric/symmetric DRAM detectionINTEL CORP·Filed 1996·Granted Sep 1, 1998·20 cites·20 claims
- 1445US6202112B1Arbitration methods to avoid deadlock and livelock when performing transactions across a bridgeINTEL CORP·Filed 1998·Granted Mar 13, 2001·19 cites·33 claims
- 1545US2003140189A1Method and apparatus for resource sharing in a multi-processor systemFiled 2002·Application pending·0 cites
- 1643US6502150B1Method and apparatus for resource sharing in a multi-processor systemINTEL CORP·Filed 1998·Granted Dec 31, 2002·12 cites·12 claims
- 1741US6157397AAGP read and CPU wire coherencyINTEL CORP·Filed 1998·Granted Dec 5, 2000·13 cites·12 claims
- 1841US6154825AMethod and apparatus for addressing a memory resource comprising memory devices having multiple configurationsINTEL CORP·Filed 1997·Granted Nov 28, 2000·13 cites·14 claims
- 1934US6173354B1Method and apparatus for decoupling internal latencies of a bus bridge from those on an external busINTEL CORP·Filed 1998·Granted Jan 9, 2001·6 cites·19 claims
- 2033US6976120B2Apparatus and method to track flag transitions for DRAM data transferINTEL CORP·Filed 2002·Granted Dec 13, 2005·0 cites·18 claims
- 2133US6385703B1Speculative request pointer advance for fast back-to-back readsINTEL CORP·Filed 1998·Granted May 7, 2002·5 cites·22 claims
- 2231US6314497B1Apparatus and method for maintaining cache coherency in a memory systemINTEL CORP·Filed 1998·Granted Nov 6, 2001·2 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →