Inventor · disambiguated record
Pidugu L. Narayana
Also filed as: NARAYANA PIDUGU · NARAYANA PIDUGU L
29 granted patents·445 citations·filing 1995–2002
97Inventor score
Top patents by PatentIndex Score
29 records- 0192US6469983B2Data packet transmission scheduling using a partitioned heapMAPLE OPTICAL SYSTEMS INC·Filed 2002·Granted Oct 22, 2002·94 cites·24 claims
- 0289US6577635B2Data packet transmission schedulingMAPLE OPTICAL SYSTEMS INC·Filed 2002·Granted Jun 10, 2003·61 cites·38 claims
- 0378US6628171B1Method, architecture and circuit for controlling and/or operating an oscillatorCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Sep 30, 2003·21 cites·18 claims
- 0472US6177843B1Oscillator circuit controlled by programmable logicCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jan 23, 2001·29 cites·11 claims
- 0571US6240031B1Memory architectureCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted May 29, 2001·18 cites·18 claims
- 0670US6400642B1Memory architectureCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 4, 2002·19 cites·19 claims
- 0767US6377071B1Composite flag generation for DDR FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Apr 23, 2002·13 cites·16 claims
- 0864US6675336B1Distributed test architecture for multiport RAMs or other circuitryCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jan 6, 2004·16 cites·16 claims
- 0951US5712992AState machine design for generating empty and full flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Jan 27, 1998·21 cites·20 claims
- 1049US5627797AFull and empty flag generator for synchronous FIFOSCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted May 6, 1997·21 cites·20 claims
- 1148US5852748AProgrammable read-write word line equality signal generation for FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Dec 22, 1998·20 cites·13 claims
- 1246US5850568ACircuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullnessCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Dec 15, 1998·16 cites·17 claims
- 1341US6070203ACircuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOSCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted May 30, 2000·10 cites·16 claims
- 1441US5809339AState machine design for generating half-full and half-empty flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Sep 15, 1998·11 cites·20 claims
- 1539US6023435AStaggered bitline precharge schemeCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Feb 8, 2000·6 cites·20 claims
- 1638US5661418ASignal generation decoder circuit and methodCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Aug 26, 1997·8 cites·24 claims
- 1737US6526470B1Fifo bus-sizing, bus-matching datapath architectureCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Feb 25, 2003·10 cites·20 claims
- 1836US5963056AFull and empty flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Oct 5, 1999·7 cites·40 claims
- 1935US6292013B1Column redundancy scheme for bus-matching fifosCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Sep 18, 2001·5 cites·20 claims
- 2035US5955897ASignal generation decoder circuit and methodCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Sep 21, 1999·6 cites·23 claims
- 2134US5994920AHalf-full flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Nov 30, 1999·5 cites·33 claims
- 2234US5991834AState machine design for generating half-full and half-empty flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Nov 23, 1999·5 cites·25 claims
- 2334US5860160AHigh speed FIFO mark and retransmit scheme using latches and prechargeCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 12, 1999·7 cites·20 claims
- 2433US6016403AState machine design for generating empty and full flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Jan 18, 2000·4 cites·37 claims
- 2533US5844423AHalf-full flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Dec 1, 1998·4 cites·20 claims
- 2631US6366979B1Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Apr 2, 2002·4 cites·18 claims
- 2731US6055177AMemory cellCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Apr 25, 2000·2 cites·19 claims
- 2828US6489805B1Circuits, architectures, and methods for generating a periodic signal in a memoryCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Dec 3, 2002·2 cites·22 claims
- 2920US6907539B1Configurage data setup/hold timing circuit with user programmable delayCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 14, 2005·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →