Inventor · disambiguated record
Simone Dario Mariani
Also filed as: MARIANI SIMONE DARIO
9 granted patents·8 pending applications·15 citations·filing 2010–2024
81Inventor score
Files withST MICROELECTRONICS SRL13ST MICROELECTRONICS INT NV2CAUSIO ALESSANDRO1MARIANI SIMONE DARIO1
Top patents by PatentIndex Score
17 records- 0190US10062757B2Semiconductor device with buried metallic region, and method for manufacturing the semiconductor deviceST MICROELECTRONICS SRL·Filed 2016·Granted Aug 28, 2018·8 cites·14 claims
- 0287US10796942B2Semiconductor structure with partially embedded insulation regionST MICROELECTRONICS SRL·Filed 2018·Granted Oct 6, 2020·4 cites·20 claims
- 0368US12463163B2Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of makingST MICROELECTRONICS SRL·Filed 2023·Granted Nov 4, 2025·0 cites·18 claims
- 0466US11469136B2Semiconductor structure with partially embedded insulation region and related methodST MICROELECTRONICS SRL·Filed 2020·Granted Oct 11, 2022·0 cites·20 claims
- 0562US2025194205A1Manufacturing method of a semiconductor electronic device with trench gateST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0659US11887948B2Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of makingST MICROELECTRONICS SRL·Filed 2021·Granted Jan 30, 2024·0 cites·23 claims
- 0759US2021143286A1Semiconductor die with buried capacitor, and method of manufacturing the semiconductor dieST MICROELECTRONICS SRL·Filed 2021·Application pending·0 cites
- 0857US8871594B2Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugationsMARIANI SIMONE DARIO·Filed 2011·Granted Oct 28, 2014·3 cites·15 claims
- 0956US10930799B2Semiconductor die with buried capacitor, and method of manufacturing the semiconductor dieST MICROELECTRONICS SRL·Filed 2019·Granted Feb 23, 2021·0 cites·13 claims
- 1055US2024332376A1Integrated electronic device with an improved conductive contact structure and related manufacturing processST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1150US9640614B2Integrated device with raised locos insulation regions and process for manufacturing such deviceST MICROELECTRONICS SRL·Filed 2014·Granted May 2, 2017·0 cites·25 claims
- 1247US2022384585A1Integrated electronic circuit including a field plate for the local reduction of the electric field and related manufacturing processST MICROELECTRONICS SRL·Filed 2022·Application pending·0 cites
- 1341US2021193658A1Integrated device with deep plug under shallow trenchST MICROELECTRONICS SRL·Filed 2020·Application pending·0 cites
- 1440US2019221652A1Semiconductor electronic device with trench gate and manufacturing method thereofST MICROELECTRONICS SRL·Filed 2019·Application pending·0 cites
- 1534US8941176B2Integrated device with raised locos insulation regions and process for manufacturing such deviceCAUSIO ALESSANDRO·Filed 2010·Granted Jan 27, 2015·0 cites·17 claims
- 1632US2014008722A1Vertical-gate mos transistor with field-plate accessST MICROELECTRONICS SRL·Filed 2013·Application pending·0 cites
- 1732US2016351495A1Process for manufacturing integrated electronic devices, in particular cmos devices using a borderless contact techniqueST MICROELECTRONICS SRL·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →