Inventor · disambiguated record
David J. Zimmerman
Also filed as: ZIMMERMAN DAVID · ZIMMERMAN DAVID J
47 granted patents·2 pending applications·775 citations·filing 1997–2020
98Inventor score
Top patents by PatentIndex Score
49 records- 0198US8607089B2Interface for storage device access over memory busQAWAMI SHEKOUFEH·Filed 2011·Granted Dec 10, 2013·58 cites·27 claims
- 0297US9317429B2Apparatus and method for implementing a multi-level memory hierarchy over common memory channelsRAMANUJAN RAJ K·Filed 2011·Granted Apr 19, 2016·92 cites·39 claims
- 0397US8862973B2Method and system for error management in a memory deviceBAINS KULJIT S·Filed 2009·Granted Oct 14, 2014·91 cites·29 claims
- 0495US9064560B2Interface for storage device access over memory busINTEL CORP·Filed 2013·Granted Jun 23, 2015·20 cites·18 claims
- 0594US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 0694US8838935B2Apparatus, method, and system for implementing micro page tablesHINTON GLENN·Filed 2010·Granted Sep 16, 2014·79 cites·25 claims
- 0794US7177211B2Memory channel test fixture and methodINTEL CORP·Filed 2003·Granted Feb 13, 2007·92 cites·37 claims
- 0893US11507430B2Accelerated resource allocation techniquesINTEL CORP·Filed 2018·Granted Nov 22, 2022·18 cites·18 claims
- 0992US9646720B2Self-repair logic for stacked memory architectureINTEL CORP·Filed 2015·Granted May 9, 2017·9 cites·28 claims
- 1092US8645777B2Boundary scan chain for stacked memoryZIMMERMAN DAVID J·Filed 2011·Granted Feb 4, 2014·10 cites·26 claims
- 1191US9418700B2Bad block management mechanismRAMANUJAN RAJ K·Filed 2012·Granted Aug 16, 2016·15 cites·19 claims
- 1290US6996749B1Method and apparatus for providing debug functionality in a buffered memory channelINTEL CORP·Filed 2003·Granted Feb 7, 2006·48 cites·25 claims
- 1389US11200176B2Dynamic partial power down of memory-side cache in a 2-level memory hierarchyINTEL CORP·Filed 2020·Granted Dec 14, 2021·2 cites·12 claims
- 1489US10347354B2Boundary scan chain for stacked memoryINTEL CORP·Filed 2016·Granted Jul 9, 2019·3 cites·21 claims
- 1588US9158619B2On chip redundancy repair for memory devicesKOBLA DARSHAN·Filed 2012·Granted Oct 13, 2015·15 cites·15 claims
- 1688US9136021B2Self-repair logic for stacked memory architectureYANG JOON-SUNG·Filed 2011·Granted Sep 15, 2015·15 cites·16 claims
- 1787US7536267B2Built-in self test for memory interconnect testingINTEL CORP·Filed 2005·Granted May 19, 2009·18 cites·9 claims
- 1887US7412627B2Method and apparatus for providing debug functionality in a buffered memory channelINTEL CORP·Filed 2005·Granted Aug 12, 2008·16 cites·25 claims
- 1986US9298573B2Built-in self-test for stacked memory architectureKOBLA DARSHAN·Filed 2012·Granted Mar 29, 2016·13 cites·21 claims
- 2086US7644250B2Defining pin functionality at device power onINTEL CORP·Filed 2006·Granted Jan 5, 2010·14 cites·26 claims
- 2183US7519891B2IO self test method and apparatus for memoryINTEL CORP·Filed 2005·Granted Apr 14, 2009·15 cites·6 claims
- 2282US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 2382US7321997B2Memory channel self testINTEL CORP·Filed 2004·Granted Jan 22, 2008·38 cites·13 claims
- 2481US9476940B2Boundary scan chain for stacked memoryINTEL CORP·Filed 2013·Granted Oct 25, 2016·5 cites·27 claims
- 2580US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
- 2680US10025737B2Interface for storage device access over memory busINTEL CORP·Filed 2015·Granted Jul 17, 2018·2 cites·20 claims
- 2776US9158616B2Method and system for error management in a memory deviceBAINS KULJIT S·Filed 2012·Granted Oct 13, 2015·4 cites·16 claims
- 2875US9922725B2Integrated circuit defect detection and repairINTEL CORP·Filed 2016·Granted Mar 20, 2018·2 cites·21 claims
- 2974US10795823B2Dynamic partial power down of memory-side cache in a 2-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Oct 6, 2020·3 cites·19 claims
- 3074US10541009B2Write data mask for power reductionINTEL CORP·Filed 2017·Granted Jan 21, 2020·3 cites·23 claims
- 3174US10504591B2Adaptive configuration of non-volatile memoryINTEL CORP·Filed 2018·Granted Dec 10, 2019·2 cites·31 claims
- 3273US7580465B2Low speed access to DRAMINTEL CORP·Filed 2005·Granted Aug 25, 2009·6 cites·10 claims
- 3371US10224115B2Self-repair logic for stacked memory architectureINTEL CORP·Filed 2017·Granted Mar 5, 2019·1 cites·25 claims
- 3471US9548137B2Integrated circuit defect detection and repairINTEL CORP·Filed 2014·Granted Jan 17, 2017·4 cites·25 claims
- 3569US7533204B2Enumeration of devices on a memory channelINTEL CORP·Filed 2006·Granted May 12, 2009·4 cites·19 claims
- 3667US9190173B2Generic data scrambler for memory circuit test engineKOBLA DARSHAN·Filed 2012·Granted Nov 17, 2015·4 cites·25 claims
- 3765US9195589B2Adaptive configuration of non-volatile memoryQAWAMI SHEKOUFEH·Filed 2011·Granted Nov 24, 2015·1 cites·25 claims
- 3861US9110134B2Input/output delay testing for devices utilizing on-chip delay generationMAK TAK M·Filed 2012·Granted Aug 18, 2015·2 cites·27 claims
- 3960US8843794B2Method, system and apparatus for evaluation of input/output buffer circuitryNELSON CHRISTOPHER J·Filed 2012·Granted Sep 23, 2014·1 cites·30 claims
- 4058US8909849B2Pipeline architecture for scalable performance on memorySUNDARAM RAJESH·Filed 2010·Granted Dec 9, 2014·2 cites·20 claims
- 4157US9564245B2Integrated circuit defect detection and repairINTEL CORP·Filed 2013·Granted Feb 7, 2017·1 cites·22 claims
- 4255US10026475B2Adaptive configuration of non-volatile memoryINTEL CORP·Filed 2015·Granted Jul 17, 2018·0 cites·26 claims
- 4355US8619883B2Low speed access to DRAMZIMMERMAN DAVID J·Filed 2009·Granted Dec 31, 2013·2 cites·7 claims
- 4452US5929448ARedundant transistor dose monitor circuit using two ICsUS AIR FORCE·Filed 1997·Granted Jul 27, 1999·18 cites·3 claims
- 4549US9036718B2Low speed access to DRAMINTEL CORP·Filed 2013·Granted May 19, 2015·0 cites·15 claims
- 4642US11238203B2Systems and methods for accessing storage-as-memoryINTEL CORP·Filed 2017·Granted Feb 1, 2022·0 cites·23 claims
- 4736US9236143B2Generic address scrambler for memory circuit test engineKOBLA DARSHAN·Filed 2011·Granted Jan 12, 2016·0 cites·17 claims
- 4836US2015187410A1Testing a wide functional interface of a device integrated on an sip without dedicated test pinsNELSON CHRISTOPHER J·Filed 2013·Application pending·0 cites
- 4933US2005080581A1Built-in self test for memory interconnect testingFiled 2003·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when David J. Zimmerman files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →