Inventor · disambiguated record
Vamsi Srikantam
Also filed as: SRIKANTAM VAMSI · SRIKANTAM VAMSI K · SRIKANTAM VAMSI KRISHNA
11 granted patents·3 pending applications·214 citations·filing 2000–2017
91Inventor score
Top patents by PatentIndex Score
14 records- 0195US7148828B2System and method for timing calibration of time-interleaved data convertersAGILENT TECHNOLOGIES INC·Filed 2005·Granted Dec 12, 2006·58 cites·22 claims
- 0286US6275083B1Low operational power, low leakage power D-type flip-flopAGILENT TECHNOLOGIES INC·Filed 2000·Granted Aug 14, 2001·41 cites·20 claims
- 0384US10318696B1Efficient techniques for process variation reduction for static timing analysisAMPERE COMPUTING LLC·Filed 2016·Granted Jun 11, 2019·7 cites·20 claims
- 0484US10318676B2Techniques for statistical frequency enhancement of statically timed designsAMPERE COMPUTING LLC·Filed 2017·Granted Jun 11, 2019·6 cites·13 claims
- 0584US6822481B1Method and apparatus for clock gating clock trees to reduce power dissipationAGILENT TECHNOLOGIES INC·Filed 2003·Granted Nov 23, 2004·41 cites·21 claims
- 0678US7450659B2Digital modulator employing a polyphase up-converter structureAGILENT TECHNOLOGIES INC·Filed 2004·Granted Nov 11, 2008·23 cites·6 claims
- 0778US7339853B2Time stamping events for fractions of a clock cycleAGILENT TECHNOLOGIES INC·Filed 2005·Granted Mar 4, 2008·11 cites·25 claims
- 0871US7085942B2Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle stateAGILENT TECHNOLOGIES INC·Filed 2003·Granted Aug 1, 2006·18 cites·33 claims
- 0963US7411437B2Triggering events at fractions of a clock cycleAGILENT TECHNOLOGIES INC·Filed 2005·Granted Aug 12, 2008·4 cites·19 claims
- 1054US7096374B2Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle stateAGILENT TECHNOLOGIES INC·Filed 2003·Granted Aug 22, 2006·5 cites·29 claims
- 1143US2007024904A1Imaging serial interface ROMBAER RICHARD L·Filed 2005·Application pending·0 cites
- 1243US2007024713A1Imaging parallel interface RAMBAER RICHARD L·Filed 2005·Application pending·0 cites
- 1341US6601230B2Low power circuit design through judicious module selectionAGILENT TECHNOLOGIES INC·Filed 2001·Granted Jul 29, 2003·0 cites·19 claims
- 1436US2007247206A1Programmable trigger delaysVOOK DIETRICH W·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →