Inventor · disambiguated record
Peter N. Ehlig
Also filed as: EHLIG PETER N
43 granted patents·3 pending applications·2,403 citations·filing 1989–2005
99Inventor score
Top patents by PatentIndex Score
46 records- 0198US5319792AModem having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next contextTEXAS INSTRUMENTS INC·Filed 1992·Granted Jun 7, 1994·159 cites·14 claims
- 0297US5142677AContext switching devices, systems and methodsTEXAS INSTRUMENTS INC·Filed 1989·Granted Aug 25, 1992·205 cites·6 claims
- 0397US5072418ASeries maxium/minimum function computing devices, systems and methodsTEXAS INSTRUMENTS INC·Filed 1989·Granted Dec 10, 1991·270 cites·28 claims
- 0496US5155812ADevices and method for generating and using systems, software waitstates on address boundaries in data processingTEXAS INSTRUMENTS INC·Filed 1989·Granted Oct 13, 1992·212 cites·20 claims
- 0595US5349687ASpeech recognition system having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next contextTEXAS INSTRUMENTS INC·Filed 1992·Granted Sep 20, 1994·168 cites·9 claims
- 0695US5319789AElectromechanical apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next contextTEXAS INSTRUMENTS INC·Filed 1992·Granted Jun 7, 1994·163 cites·20 claims
- 0793US6032268AProcessor condition sensing circuits, systems and methodsTEXAS INSTRUMENTS INC·Filed 1992·Granted Feb 29, 2000·132 cites·18 claims
- 0893US5535331AProcessor condition sensing circuits, systems and methodsTEXAS INSTRUMENTS INC·Filed 1992·Granted Jul 9, 1996·133 cites·16 claims
- 0993US5313648ASignal processing apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next contextTEXAS INSTRUMENTS INC·Filed 1992·Granted May 17, 1994·184 cites·10 claims
- 1091US6986142B1Microphone/speaker system with context switching in processorTEXAS INSTRUMENTS INC·Filed 2000·Granted Jan 10, 2006·79 cites·11 claims
- 1191US5550993AData processor with sets of two registers where both registers receive identical information and when context changes in one register the other register remains unchangedTEXAS INSTRUMENTS INC·Filed 1994·Granted Aug 27, 1996·103 cites·17 claims
- 1288US6546505B1Processor condition sensing circuits, systems and methodsTEXAS INSTRUMENTS INC·Filed 1999·Granted Apr 8, 2003·46 cites·13 claims
- 1386US6134578AData processing device and method of operation with context switchingTEXAS INSTRUMENTS INC·Filed 1996·Granted Oct 17, 2000·80 cites·11 claims
- 1479US6918025B2IC with wait state registersTEXAS INSTRUMENTS INC·Filed 2003·Granted Jul 12, 2005·12 cites·28 claims
- 1575US6996747B2Program counter trace stack, access port, and serial scan pathTEXAS INSTRUMENTS INC·Filed 2003·Granted Feb 7, 2006·14 cites·9 claims
- 1675US5907714AMethod for pipelined data processing with conditioning instructions for controlling execution of instructions without pipeline flushingTEXAS INSTRUMENTS INC·Filed 1994·Granted May 25, 1999·31 cites·10 claims
- 1772US5946483ADevices, systems and methods for conditional instructionsTEXAS INSTRUMENTS INC·Filed 1997·Granted Aug 31, 1999·29 cites·4 claims
- 1872US5617574ADevices, systems and methods for conditional instructionsTEXAS INSTRUMENTS INC·Filed 1994·Granted Apr 1, 1997·27 cites·17 claims
- 1972US5101498APin selectable multi-mode processorTEXAS INSTRUMENTS INC·Filed 1990·Granted Mar 31, 1992·36 cites·35 claims
- 2070US6334181B1DSP with wait state registers having at least two portionsTEXAS INSTRUMENTS INC·Filed 1999·Granted Dec 25, 2001·27 cites·3 claims
- 2167US5579497ADevices and systems with parallel logic unit, and methodsTEXAS INSTRUMENTS INC·Filed 1995·Granted Nov 26, 1996·20 cites·2 claims
- 2265US6253307B1Data processing device with mask and status bits for selecting a set of status conditionsTEXAS INSTRUMENTS INC·Filed 1994·Granted Jun 26, 2001·19 cites·19 claims
- 2363US6986028B2Repeat block with zero cycle overhead nestingTEXAS INSTRUMENTS INC·Filed 2002·Granted Jan 10, 2006·9 cites·10 claims
- 2462US5579218ADevices and systems with parallel logic unit, and methodsTEXAS INSTRUMENTS INC·Filed 1995·Granted Nov 26, 1996·29 cites·4 claims
- 2561US5652910ADevices and systems with conditional instructionsTEXAS INSTRUMENTS INC·Filed 1995·Granted Jul 29, 1997·39 cites·6 claims
- 2655US6768669B2Volatile memory cell reconfigured as a non-volatile memory cellTEXAS INSTRUMENTS INC·Filed 2002·Granted Jul 27, 2004·10 cites·12 claims
- 2753US6567910B2Digital signal processing unit with emulation circuitry and debug interrupt enable register indicating serviceable time-critical interrupts during real-time emulation modeTEXAS INSTRUMENTS INC·Filed 1999·Granted May 20, 2003·31 cites·14 claims
- 2851US6263419B1Integrated circuit with wait state registersTEXAS INSTRUMENTS INC·Filed 1999·Granted Jul 17, 2001·10 cites·6 claims
- 2949US6311264B1Digital signal processor with wait state registerTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 30, 2001·9 cites·8 claims
- 3049US2006059387A1Processor condition sensing circuits, systems and methodsSWOBODA GARY L·Filed 2005·Application pending·0 cites
- 3148US5829054ADevices and systems with parallel logic unit operable on data memory locationsTEXAS INSTRUMENTS INC·Filed 1997·Granted Oct 27, 1998·20 cites·55 claims
- 3247US5109494APassive processor communications interfaceTEXAS INSTRUMENTS INC·Filed 1990·Granted Apr 28, 1992·20 cites·19 claims
- 3347US2005251638A1Devices, systems and methods for conditional instructionsBOUTAUD FREDERIC·Filed 2004·Application pending·0 cites
- 3446US5551050ASystem and method using synchronized processors to perform real time internal monitoring of a data processing deviceTEXAS INSTRUMENTS INC·Filed 1994·Granted Aug 27, 1996·16 cites·2 claims
- 3545US5586275ADevices and systems with parallel logic unit operable on data memory locations, and methodsTEXAS INSTRUMENTS INC·Filed 1994·Granted Dec 17, 1996·10 cites·17 claims
- 3643US6263418B1Process of operating a microprocessor to use wait state numbersTEXAS INSTRUMENTS INC·Filed 1999·Granted Jul 17, 2001·6 cites·3 claims
- 3743US6249859B1IC with wait state registersTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 19, 2001·6 cites·6 claims
- 3843US2005278512A1Context switching devices, systems and methodsEHLIG PETER N·Filed 2005·Application pending·0 cites
- 3941US6249860B1System with wait state registersTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 19, 2001·5 cites·7 claims
- 4041US6240505B1System with wait state registersTEXAS INSTRUMENTS INC·Filed 1999·Granted May 29, 2001·5 cites·2 claims
- 4141US5583767ADevices and systems with parallel logic unit, and methods noticeTEXAS INSTRUMENTS INC·Filed 1995·Granted Dec 10, 1996·9 cites·4 claims
- 4240US6243801B1System with wait state registersTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 5, 2001·5 cites·6 claims
- 4338US5828577ADevices and systems with protective terminal configuration, and methodsTEXAS INSTRUMENTS INC·Filed 1995·Granted Oct 27, 1998·7 cites·3 claims
- 4437US6247111B1System with wait state registerTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 12, 2001·3 cites·5 claims
- 4534US5724248ADevices and systems with protective terminal configuration, and methodsTEXAS INSTRUMENTS INC·Filed 1992·Granted Mar 3, 1998·4 cites·38 claims
- 4631US5777885ADevices and systems with protective terminal configuration, and methodsTEXAS INSTRUMENTS INC·Filed 1995·Granted Jul 7, 1998·1 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →