Inventor · disambiguated record
Tomasz Czajkowski
Also filed as: CZAJKOWSKI TOMASZ · CZAJKOWSKI TOMASZ S · CZAJKOWSKI TOMASZ SEBASTIAN
17 granted patents·3 pending applications·67 citations·filing 2012–2023
91Inventor score
Top patents by PatentIndex Score
20 records- 0192US9904514B1Fused floating-point arithmetic circuitryALTERA CORP·Filed 2015·Granted Feb 27, 2018·12 cites·20 claims
- 0288US10049082B2Dot product based processing elementsALTERA CORP·Filed 2016·Granted Aug 14, 2018·6 cites·16 claims
- 0387US10599404B1M/A for compiling parallel program having barrier synchronization for programmable hardwareNETO DAVID·Filed 2012·Granted Mar 24, 2020·17 cites·27 claims
- 0486US11328037B2Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliersINTEL CORP·Filed 2017·Granted May 10, 2022·5 cites·21 claims
- 0586US10339201B1Dot product based processing elementsALTERA CORP·Filed 2018·Granted Jul 2, 2019·4 cites·26 claims
- 0686US9400635B1Methods and apparatus for performing dynamic data alignment for floating-point operationsALTERA CORP·Filed 2013·Granted Jul 26, 2016·10 cites·23 claims
- 0780US10007487B1Double-precision floating-point operationALTERA CORP·Filed 2016·Granted Jun 26, 2018·3 cites·15 claims
- 0872US9626218B1Repartitioning and reordering of multiple threads into subsets based on possible access conflict, for sequential access to groups of memory banks in a shared memoryALTERA CORP·Filed 2014·Granted Apr 18, 2017·3 cites·20 claims
- 0972US9424043B1Forward-flow selectionALTERA CORP·Filed 2012·Granted Aug 23, 2016·3 cites·20 claims
- 1071US2023359695A1Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix MultipliersINTEL CORP·Filed 2023·Application pending·0 cites
- 1169US9639326B2Floating-point adder circuitryALTERA CORP·Filed 2016·Granted May 2, 2017·1 cites·22 claims
- 1266US2023064381A1Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix MultipliersINTEL CORP·Filed 2022·Application pending·0 cites
- 1362US9696991B1Fixed-point and floating-point optimizationALTERA CORP·Filed 2012·Granted Jul 4, 2017·1 cites·18 claims
- 1462US9430425B1Multi-cycle resource sharingALTERA CORP·Filed 2012·Granted Aug 30, 2016·1 cites·20 claims
- 1559US9135087B1Workgroup handling in pipelined circuitsALTERA CORP·Filed 2012·Granted Sep 15, 2015·1 cites·19 claims
- 1654US9405728B2Floating-point adder circuitryALTERA CORP·Filed 2013·Granted Aug 2, 2016·0 cites·21 claims
- 1753US11816488B2Method and apparatus for dynamically simplifying processor instructionsHUAWEI TECH CO LTD·Filed 2021·Granted Nov 14, 2023·0 cites·12 claims
- 1852US11755299B2Method and apparatus for functional unit balancing at program compile timeHUAWEI TECH CO LTD·Filed 2021·Granted Sep 12, 2023·0 cites·27 claims
- 1951US11256836B2Toggle rate reduction in high level programming implementationsINTEL CORP·Filed 2017·Granted Feb 22, 2022·0 cites·12 claims
- 2040US2024012646A1System and method of prefetching array segmentsHUAWEI TECH CO LTD·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →