Inventor · disambiguated record
Michael J. Colwell
Also filed as: COLWELL MICHAEL · COLWELL MICHAEL J
14 granted patents·909 citations·filing 1994–2004
95Inventor score
Top patents by PatentIndex Score
14 records- 0197US6617621B1Gate array architecture using elevated metal levels for customizationVIRAGE LOGIC CORP·Filed 2000·Granted Sep 9, 2003·229 cites·53 claims
- 0292US5698873AHigh density gate array base cell architectureLSI LOGIC CORP·Filed 1996·Granted Dec 16, 1997·129 cites·33 claims
- 0391US5917207AProgrammable polysilicon gate array base cell architectureLSI LOGIC CORP·Filed 1997·Granted Jun 29, 1999·135 cites·20 claims
- 0488US7129562B1Dual-height cell with variable width power rail architectureVIRAGE LOGIC CORP·Filed 2004·Granted Oct 31, 2006·43 cites·6 claims
- 0588US6838713B1Dual-height cell with variable width power rail architectureVIRAGE LOGIC CORP·Filed 1999·Granted Jan 4, 2005·68 cites·22 claims
- 0682US5728612AMethod for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed therebyLSI LOGIC CORP·Filed 1996·Granted Mar 17, 1998·51 cites·4 claims
- 0781US5670890ASwitchable pull-ups and pull-downs for IDDQ testing of integrated circuitsLSI LOGIC CORP·Filed 1995·Granted Sep 23, 1997·55 cites·20 claims
- 0877US5843813AI/O driver design for simultaneous switching noise minimization and ESD performance enhancementLSI LOGIC CORP·Filed 1996·Granted Dec 1, 1998·38 cites·5 claims
- 0977US5552333AMethod for designing low profile variable width input/output cellsLSI LOGIC CORP·Filed 1994·Granted Sep 3, 1996·36 cites·10 claims
- 1072US5644251ASwitchable pull-ups and pull-downs for IDDQ testing of integrated circuitsLSI LOGIC CORP·Filed 1995·Granted Jul 1, 1997·35 cites·33 claims
- 1168US5760428AVariable width low profile gate array input/output architectureLSI LOGIC CORP·Filed 1996·Granted Jun 2, 1998·43 cites·47 claims
- 1262US5777354ALow profile variable width input/output cellsLSI LOGIC CORP·Filed 1997·Granted Jul 7, 1998·19 cites·19 claims
- 1356US5773855AMicroelectronic circuit including silicided field-effect transistor elements that bifunction as interconnectsLSI LOGIC CORP·Filed 1997·Granted Jun 30, 1998·17 cites·12 claims
- 1444US5691218AMethod of fabricating a programmable polysilicon gate array base cell structureLSI LOGIC CORP·Filed 1996·Granted Nov 25, 1997·11 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →