Inventor · disambiguated record
Arthur Hunter
Also filed as: HUNTER ARTHUR · HUNTER ARTHUR D · HUNTER ARTHUR D JR · HUNTER JR ARTHUR
29 granted patents·13 pending applications·166 citations·filing 2000–2025
96Inventor score
Top patents by PatentIndex Score
42 records- 0198US11676239B2Sparse optimizations for a matrix accelerator architectureINTEL CORP·Filed 2021·Granted Jun 13, 2023·10 cites·20 claims
- 0298US11620256B2Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2022·Granted Apr 4, 2023·36 cites·22 claims
- 0398US11113784B2Sparse optimizations for a matrix accelerator architectureINTEL CORP·Filed 2020·Granted Sep 7, 2021·46 cites·25 claims
- 0497US12182062B1Multi-tile memory managementINTEL CORP·Filed 2022·Granted Dec 31, 2024·2 cites·20 claims
- 0595US12013808B2Multi-tile architecture for graphics operationsINTEL CORP·Filed 2020·Granted Jun 18, 2024·3 cites·17 claims
- 0694US10909039B2Data prefetching for graphics data processingINTEL CORP·Filed 2019·Granted Feb 2, 2021·5 cites·21 claims
- 0793US2025103548A1Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2024·Application pending·0 cites
- 0892US2025004981A1Multi-tile memory managementINTEL CORP·Filed 2024·Application pending·0 cites
- 0990US12210477B2Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2020·Granted Jan 28, 2025·2 cites·20 claims
- 1090US11145105B2Multi-tile graphics processor renderingINTEL CORP·Filed 2019·Granted Oct 12, 2021·6 cites·14 claims
- 1190US7685346B2Demotion-based arbitrationINTEL CORP·Filed 2007·Granted Mar 23, 2010·26 cites·5 claims
- 1290US2024320184A1Multi-tile architecture for graphics operationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1387US12094048B2Multi-tile graphics processor renderingINTEL CORP·Filed 2021·Granted Sep 17, 2024·1 cites·15 claims
- 1487US10963985B2Mesh shader output management technologyINTEL CORP·Filed 2019·Granted Mar 30, 2021·5 cites·24 claims
- 1582US12293431B2Sparse optimizations for a matrix accelerator architectureINTEL CORP·Filed 2023·Granted May 6, 2025·0 cites·20 claims
- 1682US2025046001A1Multi-tile graphics processor renderingINTEL CORP·Filed 2024·Application pending·0 cites
- 1782US2024256456A1Data prefetching for graphics data processingINTEL CORP·Filed 2023·Application pending·0 cites
- 1881US2025209564A1Sparse optimizations for a matrix accelerator architectureINTEL CORP·Filed 2025·Application pending·0 cites
- 1976US12099461B2Multi-tile memory managementINTEL CORP·Filed 2020·Granted Sep 24, 2024·0 cites·21 claims
- 2076US11892950B2Data prefetching for graphics data processingINTEL CORP·Filed 2022·Granted Feb 6, 2024·0 cites·13 claims
- 2171US2025078198A1Tessellation redistribution for reducing latencies in processorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2270US11409658B2Data prefetching for graphics data processingINTEL CORP·Filed 2021·Granted Aug 9, 2022·0 cites·18 claims
- 2368US7346716B2Tracking progress of data streamerINTEL CORP·Filed 2003·Granted Mar 18, 2008·13 cites·12 claims
- 2467US11508338B2Register spill/fill using shared local memory spaceINTEL CORP·Filed 2020·Granted Nov 22, 2022·0 cites·10 claims
- 2567US11354768B2Intelligent graphics dispatching mechanismINTEL CORP·Filed 2020·Granted Jun 7, 2022·0 cites·20 claims
- 2667US8140781B2Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technologyTEH CHEE HAK·Filed 2007·Granted Mar 20, 2012·4 cites·17 claims
- 2765US10796667B2Register spill/fill using shared local memory spaceINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·17 claims
- 2864US10565675B2Intelligent graphics dispatching mechanismINTEL CORP·Filed 2019·Granted Feb 18, 2020·0 cites·25 claims
- 2963US12499503B2Multi-render partitioningINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 3060US12125121B2Tessellation redistribution for reducing latencies in processorsINTEL CORP·Filed 2021·Granted Oct 22, 2024·0 cites·20 claims
- 3159US10235736B2Intelligent graphics dispatching mechanismINTEL CORP·Filed 2017·Granted Mar 19, 2019·0 cites·21 claims
- 3259US7694044B2Stream under-run/over-run recoveryINTEL CORP·Filed 2008·Granted Apr 6, 2010·2 cites·12 claims
- 3357US10453427B2Register spill/fill using shared local memory spaceINTEL CORP·Filed 2017·Granted Oct 22, 2019·0 cites·16 claims
- 3456US7370125B2Stream under-run/over-run recoveryINTEL CORP·Filed 2003·Granted May 6, 2008·5 cites·14 claims
- 3555US2025147762A1Multiple register allocation sizes for gpu hardware threadsINTEL CORP·Filed 2023·Application pending·0 cites
- 3648US2023297421A1Hard partitioning via intra-soc compositionINTEL CORP·Filed 2022·Application pending·0 cites
- 3742US10217270B2Scalable geometry processing within a checkerboard multi-GPU configurationINTEL CORP·Filed 2017·Granted Feb 26, 2019·0 cites·25 claims
- 3842US2006074619A1Recognizing signals in design simulationINTEL CORP·Filed 2005·Application pending·0 cites
- 3942US2005160188A1Method and apparatus to manage memory access requestsFiled 2004·Application pending·0 cites
- 4041US2005143843A1Command pacingFiled 2003·Application pending·0 cites
- 4139US2022414815A1Sort middle architecture for multiple graphics processing unitsINTEL CORP·Filed 2021·Application pending·0 cites
- 4237US6993468B2Recognizing signals in design simulationINTEL CORP·Filed 2000·Granted Jan 31, 2006·0 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →