Inventor · disambiguated record
John D. Irish
Also filed as: IRISH JOHN · IRISH JOHN D · IRISH JOHN DAVID
50 granted patents·16 pending applications·560 citations·filing 1990–2019
98Inventor score
Top patents by PatentIndex Score
66 records- 0195US10761995B2Integrated circuit and data processing system having a configurable cache directory for an acceleratorIBM·Filed 2019·Granted Sep 1, 2020·11 cites·20 claims
- 0295US9342387B1Hardware-assisted interthread push communicationIBM·Filed 2015·Granted May 17, 2016·13 cites·6 claims
- 0392US9286148B1Hardware-assisted interthread push communicationIBM·Filed 2014·Granted Mar 15, 2016·13 cites·13 claims
- 0488US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 0587US5168571ASystem for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte dataIBM·Filed 1990·Granted Dec 1, 1992·161 cites·4 claims
- 0684US9575825B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Feb 21, 2017·6 cites·10 claims
- 0780US6314491B1Peer-to-peer cache moves in a multiprocessor data processing systemIBM·Filed 1999·Granted Nov 6, 2001·95 cites·22 claims
- 0877US11113204B2Translation invalidation in a translation cache serving an acceleratorIBM·Filed 2019·Granted Sep 7, 2021·1 cites·20 claims
- 0977US7840744B2Rank select operation between an XIO interface and a double data rate interfaceIBM·Filed 2007·Granted Nov 23, 2010·8 cites·18 claims
- 1076US7757040B2Memory command and address conversion between an XDR interface and a double data rate interfaceIBM·Filed 2007·Granted Jul 13, 2010·8 cites·22 claims
- 1176US7382777B2Method for implementing actions based on packet classification and lookup resultsIBM·Filed 2003·Granted Jun 3, 2008·22 cites·6 claims
- 1272US9766890B2Non-serialized push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Sep 19, 2017·2 cites·14 claims
- 1372US9678812B2Addressing for inter-thread push communicationIBM·Filed 2014·Granted Jun 13, 2017·2 cites·12 claims
- 1472US7716423B2Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modesIBM·Filed 2006·Granted May 11, 2010·5 cites·10 claims
- 1570US5790838APipelined memory interface and method for using the sameIBM·Filed 1996·Granted Aug 4, 1998·30 cites·19 claims
- 1668US7634591B2Method and apparatus for tracking command order dependenciesIBM·Filed 2006·Granted Dec 15, 2009·4 cites·5 claims
- 1768US6151664AProgrammable SRAM and DRAM cache interface with preset access prioritiesIBM·Filed 1999·Granted Nov 21, 2000·50 cites·26 claims
- 1867US9684551B2Addressing for inter-thread push communicationIBM·Filed 2015·Granted Jun 20, 2017·1 cites·5 claims
- 1967US5751990AAbridged virtual address cache directoryIBM·Filed 1994·Granted May 12, 1998·48 cites·18 claims
- 2065US11030110B2Integrated circuit and data processing system supporting address aliasing in an acceleratorIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 2165US10846235B2Integrated circuit and data processing system supporting attachment of a real address-agnostic acceleratorIBM·Filed 2019·Granted Nov 24, 2020·0 cites·16 claims
- 2264US8327075B2Methods and apparatus for handling a cache missIRISH JOHN D·Filed 2005·Granted Dec 4, 2012·3 cites·12 claims
- 2362US8792332B2Implementing lane shuffle for fault-tolerant communication linksHECKENDORF RYAN ABEL·Filed 2010·Granted Jul 29, 2014·2 cites·14 claims
- 2462US7721023B2I/O address translation method for specifying a relaxed ordering for I/O accessesIBM·Filed 2005·Granted May 18, 2010·2 cites·16 claims
- 2561US7917700B2Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency stateIBM·Filed 2007·Granted Mar 29, 2011·2 cites·16 claims
- 2660US6922753B2Cache prefetchingIBM·Filed 2002·Granted Jul 26, 2005·7 cites·16 claims
- 2758US7809008B2Methods and apparatus for routing packetsIBM·Filed 2008·Granted Oct 5, 2010·1 cites·7 claims
- 2858US7539840B2Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2006·Granted May 26, 2009·1 cites·6 claims
- 2957US7194586B2Method and apparatus for implementing cache state as history of read/write shared dataIBM·Filed 2002·Granted Mar 20, 2007·5 cites·15 claims
- 3056US8490102B2Resource allocation management using IOC token requestor logicHANDLOGTEN GLEN H·Filed 2004·Granted Jul 16, 2013·6 cites·28 claims
- 3156US8127082B2Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operationsMCBRIDE CHAD B·Filed 2006·Granted Feb 28, 2012·2 cites·23 claims
- 3256US7096362B2Internet authentication with multiple independent certificate authoritiesIBM·Filed 2001·Granted Aug 22, 2006·5 cites·18 claims
- 3355US7746777B2Centralized bandwidth management method and apparatusIBM·Filed 2003·Granted Jun 29, 2010·4 cites·19 claims
- 3454US7757006B2Implementing conditional packet alterations based on transmit portIBM·Filed 2008·Granted Jul 13, 2010·0 cites·8 claims
- 3554US6000011AMulti-entry fully associative transition cacheIBM·Filed 1996·Granted Dec 7, 1999·29 cites·33 claims
- 3653US7362753B2Method and hardware apparatus for implementing frame alteration commandsIBM·Filed 2003·Granted Apr 22, 2008·3 cites·9 claims
- 3753US2009187695A1Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2009·Application pending·0 cites
- 3852US9778933B2Non-serialized push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2015·Granted Oct 3, 2017·0 cites·8 claims
- 3951US9569293B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2015·Granted Feb 14, 2017·0 cites·5 claims
- 4051US7660908B2Implementing virtual packet storage via packet work areaIBM·Filed 2003·Granted Feb 9, 2010·1 cites·9 claims
- 4150US8589630B2Methods and apparatus for handling a cache missIRISH JOHN D·Filed 2012·Granted Nov 19, 2013·0 cites·20 claims
- 4250US7961732B2Method and hardware apparatus for implementing frame alteration commandsIBM·Filed 2008·Granted Jun 14, 2011·0 cites·9 claims
- 4350US7411956B2Methods and apparatus for routing packetsIBM·Filed 2003·Granted Aug 12, 2008·1 cites·27 claims
- 4450US7089387B2Methods and apparatus for maintaining coherency in a multi-processor systemIBM·Filed 2003·Granted Aug 8, 2006·1 cites·29 claims
- 4550US2008198853A1Apparatus for implementing actions based on packet classification and lookup resultsIBM·Filed 2008·Application pending·0 cites
- 4649US10613979B2Accelerator memory coherency with single state machineIBM·Filed 2017·Granted Apr 7, 2020·0 cites·20 claims
- 4748US7475161B2Implementing conditional packet alterations based on transmit portIBM·Filed 2003·Granted Jan 6, 2009·0 cites·4 claims
- 4848US7330478B2Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processorIBM·Filed 2003·Granted Feb 12, 2008·0 cites·5 claims
- 4946US8170024B2Implementing pointer and stake model for frame alteration code in a network processorIMMING KERRY CHRISTOPHER·Filed 2007·Granted May 1, 2012·0 cites·13 claims
- 5046US7248595B2Method, apparatus, and computer program product for implementing packet orderingIBM·Filed 2003·Granted Jul 24, 2007·0 cites·12 claims
Showing the top 50 of 66 patent records by PatentIndex Score.
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